Support debug system bus access.

[riscv-isa-sim.git] / riscv / rocc.h

diff --git a/riscv/rocc.h b/riscv/rocc.h
index 6deccf8d9b6cd1539879e62149200139141d17d2..63d074d41c084ef58402152a926656e38121815f 100644 (file)
--- a/riscv/rocc.h
+++ b/riscv/rocc.h
@@ -6,13 +6,19 @@
 struct rocc_insn_t
 {
   unsigned opcode : 7;
+  unsigned rd : 5;
   unsigned xs2 : 1;
   unsigned xs1 : 1;
   unsigned xd : 1;
-  unsigned funct : 7;
-  unsigned rs2 : 5;
   unsigned rs1 : 5;
-  unsigned rd : 5;
+  unsigned rs2 : 5;
+  unsigned funct : 7;
+};
+
+union rocc_insn_union_t
+{
+  rocc_insn_t r;
+  insn_t i;
 };
 
 class rocc_t : public extension_t
@@ -23,6 +29,7 @@ class rocc_t : public extension_t
   virtual reg_t custom2(rocc_insn_t insn, reg_t xs1, reg_t xs2);
   virtual reg_t custom3(rocc_insn_t insn, reg_t xs1, reg_t xs2);
   std::vector<insn_desc_t> get_instructions();
+  std::vector<disasm_insn_t*> get_disasms();
 };
 
 #endif