sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
std::vector<std::pair<reg_t, mem_t*>> mems,
- const std::vector<std::string>& args)
- : htif_t(args), debug_module(this), mems(mems), procs(std::max(nprocs, size_t(1))),
- start_pc(start_pc),
- current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
+ const std::vector<std::string>& args,
+ std::vector<int> const hartids, unsigned progsize,
+ unsigned max_bus_master_bits, bool require_authentication)
+ : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
+ start_pc(start_pc), current_step(0), current_proc(0), debug(false),
+ remote_bitbang(NULL),
+ debug_module(this, progsize, max_bus_master_bits, require_authentication)
{
signal(SIGINT, &handle_signal);
debug_mmu = new mmu_t(this, NULL);
- for (size_t i = 0; i < procs.size(); i++) {
- procs[i] = new processor_t(isa, this, i, halted);
+ if (hartids.size() == 0) {
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, i, halted);
+ }
+ }
+ else {
+ if (hartids.size() != procs.size()) {
+ std::cerr << "Number of specified hartids doesn't match number of processors" << strerror(errno) << std::endl;
+ exit(1);
+ }
+ for (size_t i = 0; i < procs.size(); i++) {
+ procs[i] = new processor_t(isa, this, hartids[i], halted);
+ }
}
clint.reset(new clint_t(procs));
const int reset_vec_size = 8;
start_pc = start_pc == reg_t(-1) ? get_entry_point() : start_pc;
- reg_t pc_delta = start_pc - DEFAULT_RSTVEC;
- reg_t pc_delta_hi = (pc_delta + 0x800U) & ~reg_t(0xfffU);
- reg_t pc_delta_lo = pc_delta - pc_delta_hi;
- if ((pc_delta_hi >> 31) != 0 && (pc_delta_hi >> 31) != reg_t(-1) >> 31) {
- fprintf(stderr, "initial pc %" PRIx64 " out of range\n", pc_delta);
- abort();
- }
uint32_t reset_vec[reset_vec_size] = {
- 0x297 + uint32_t(pc_delta_hi), // auipc t0, &pc
- 0x597, // auipc a1, &dtb
- 0x58593 + ((reset_vec_size - 1) * 4 << 20), // addi a1, a1, &dtb
- 0xf1402573, // csrr a0, mhartid
- 0x28067 + uint32_t(pc_delta_lo << 20) // jalr zero, t0, &pc
+ 0x297, // auipc t0,0x0
+ 0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
+ 0xf1402573, // csrr a0, mhartid
+ get_core(0)->get_xlen() == 32 ?
+ 0x0182a283u : // lw t0,24(t0)
+ 0x0182b283u, // ld t0,24(t0)
+ 0x28067, // jr t0
+ 0,
+ (uint32_t) (start_pc & 0xffffffff),
+ (uint32_t) (start_pc >> 32)
};
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
" reg = <" << i << ">;\n"
" status = \"okay\";\n"
" compatible = \"riscv\";\n"
- " riscv,isa = \"" << procs[i]->isa_string << "\";\n"
- " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
+ " riscv,isa = \"" << procs[i]->get_isa_string() << "\";\n"
+ " mmu-type = \"riscv," << (procs[i]->get_max_xlen() <= 32 ? "sv32" : "sv48") << "\";\n"
" clock-frequency = <" << CPU_HZ << ">;\n"
" CPU" << i << "_intc: interrupt-controller {\n"
" #interrupt-cells = <1>;\n"
" 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
" };\n"
" };\n"
+ " htif {\n"
+ " compatible = \"ucb,htif0\";\n"
+ " };\n"
"};\n";
dts = s.str();
memcpy(&data, src, sizeof data);
debug_mmu->store_uint64(taddr, data);
}
+
+void sim_t::proc_reset(unsigned id)
+{
+ debug_module.proc_reset(id);
+}