Generate device tree for target machine

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 59fe593b92d45dd730392fc9705b4aa696b0fe43..67b655e6634d79cc7ea033d691ab89dd95f867c2 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -2,6 +2,7 @@
 
 #include "sim.h"
 #include "htif.h"
+#include "devicetree.h"
 #include <map>
 #include <iostream>
 #include <climits>
@@ -18,9 +19,10 @@ static void handle_signal(int sig)
   signal(sig, &handle_signal);
 }
 
-sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
+sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
+             const std::vector<std::string>& args)
   : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
-    current_step(0), current_proc(0), debug(false)
+    rtc(0), current_step(0), current_proc(0), debug(false)
 {
   signal(SIGINT, &handle_signal);
   // allocate target machine's memory, shrinking it as necessary
@@ -41,27 +43,19 @@ sim_t::sim_t(size_t nprocs, size_t mem_mb, const std::vector<std::string>& args)
   debug_mmu = new mmu_t(mem, memsz);
 
   for (size_t i = 0; i < procs.size(); i++)
-    procs[i] = new processor_t(this, new mmu_t(mem, memsz), i);
+    procs[i] = new processor_t(isa, this, i);
+
+  make_device_tree();
 }
 
 sim_t::~sim_t()
 {
   for (size_t i = 0; i < procs.size(); i++)
-  {
-    mmu_t* pmmu = procs[i]->get_mmu();
     delete procs[i];
-    delete pmmu;
-  }
   delete debug_mmu;
   free(mem);
 }
 
-void sim_t::send_ipi(reg_t who)
-{
-  if (who < procs.size())
-    procs[who]->deliver_ipi();
-}
-
 reg_t sim_t::get_scr(int which)
 {
   switch (which)
@@ -74,6 +68,8 @@ reg_t sim_t::get_scr(int which)
 
 int sim_t::run()
 {
+  if (!debug && log)
+    set_procs_debug(true);
   while (htif->tick())
   {
     if (debug || ctrlc_pressed)
@@ -96,8 +92,10 @@ void sim_t::step(size_t n)
     {
       current_step = 0;
       procs[current_proc]->yield_load_reservation();
-      if (++current_proc == procs.size())
+      if (++current_proc == procs.size()) {
         current_proc = 0;
+        rtc += INTERLEAVE / INSNS_PER_RTC_TICK;
+      }
 
       htif->tick();
     }
@@ -124,8 +122,73 @@ void sim_t::set_debug(bool value)
   debug = value;
 }
 
+void sim_t::set_log(bool value)
+{
+  log = value;
+}
+
+void sim_t::set_histogram(bool value)
+{
+  histogram_enabled = value;
+  for (size_t i = 0; i < procs.size(); i++) {
+    procs[i]->set_histogram(histogram_enabled);
+  }
+}
+
 void sim_t::set_procs_debug(bool value)
 {
   for (size_t i=0; i< procs.size(); i++)
     procs[i]->set_debug(value);
 }
+
+bool sim_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes)
+{
+  if (addr + len < addr)
+    return false;
+  return bus.load(addr, len, bytes);
+}
+
+bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
+{
+  if (addr + len < addr)
+    return false;
+  return bus.store(addr, len, bytes);
+}
+
+void sim_t::make_device_tree()
+{
+  char buf[32];
+  size_t max_devtree_size = procs.size() * 4096; // sloppy upper bound
+  size_t cpu_size = NCSR * procs[0]->max_xlen / 8;
+  reg_t cpu_addr = memsz + max_devtree_size;
+
+  device_tree dt;
+  dt.begin_node("");
+  dt.add_prop("#address-cells", 2);
+  dt.add_prop("#size-cells", 2);
+  dt.add_prop("model", "Spike");
+    dt.begin_node("memory@0");
+      dt.add_prop("device_type", "memory");
+      dt.add_reg({0, memsz});
+    dt.end_node();
+    dt.begin_node("cpus");
+      dt.add_prop("#address-cells", 2);
+      dt.add_prop("#size-cells", 2);
+      for (size_t i = 0; i < procs.size(); i++) {
+        sprintf(buf, "cpu@%" PRIx64, cpu_addr);
+        dt.begin_node(buf);
+          dt.add_prop("device_type", "cpu");
+          dt.add_prop("compatible", "riscv");
+          dt.add_prop("isa", procs[i]->isa);
+          dt.add_reg({cpu_addr});
+        dt.end_node();
+
+        bus.add_device(cpu_addr, procs[i]);
+        cpu_addr += cpu_size;
+      }
+    dt.end_node();
+  dt.end_node();
+
+  devicetree.reset(new rom_device_t(dt.finalize()));
+  bus.add_device(memsz, devicetree.get());
+}