Add writable ibuf and data registers.

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 0e7c3871841099c78e391d4835533cb70e576c52..86e23b0908650b7ac45caf6a336cc3fc000bf369 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -2,7 +2,7 @@
 
 #include "sim.h"
 #include "mmu.h"
-#include "gdbserver.h"
+#include "remote_bitbang.h"
 #include <map>
 #include <iostream>
 #include <sstream>
@@ -23,7 +23,7 @@ static void handle_signal(int sig)
 sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
              const std::vector<std::string>& args)
   : htif_t(args), procs(std::max(nprocs, size_t(1))),
-    current_step(0), current_proc(0), debug(false), gdbserver(NULL)
+    current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
 {
   signal(SIGINT, &handle_signal);
   // allocate target machine's memory, shrinking it as necessary
@@ -38,8 +38,8 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
     memsz = (size_t)(memsz*0.9)/quantum*quantum;
 
   if (memsz != memsz0)
-    fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
-            (unsigned long)memsz, (unsigned long)memsz0);
+    fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
+            memsz, memsz0);
 
   bus.add_device(DEBUG_START, &debug_module);
 
@@ -77,8 +77,8 @@ void sim_t::main()
       interactive();
     else
       step(INTERLEAVE);
-    if (gdbserver) {
-      gdbserver->handle();
+    if (remote_bitbang) {
+      remote_bitbang->tick();
     }
   }
 }