Add writable ibuf and data registers.

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index a4ae309a7240f97fe3bf9cde565bce167d2a166d..86e23b0908650b7ac45caf6a336cc3fc000bf369 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -2,7 +2,7 @@
 
 #include "sim.h"
 #include "mmu.h"
-#include "htif.h"
+#include "remote_bitbang.h"
 #include <map>
 #include <iostream>
 #include <sstream>
@@ -20,10 +20,10 @@ static void handle_signal(int sig)
   signal(sig, &handle_signal);
 }
 
-sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
+sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
              const std::vector<std::string>& args)
-  : htif(new htif_isasim_t(this, args)), procs(std::max(nprocs, size_t(1))),
-    current_step(0), current_proc(0), debug(false)
+  : htif_t(args), procs(std::max(nprocs, size_t(1))),
+    current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
 {
   signal(SIGINT, &handle_signal);
   // allocate target machine's memory, shrinking it as necessary
@@ -38,13 +38,16 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb,
     memsz = (size_t)(memsz*0.9)/quantum*quantum;
 
   if (memsz != memsz0)
-    fprintf(stderr, "warning: only got %lu bytes of target mem (wanted %lu)\n",
-            (unsigned long)memsz, (unsigned long)memsz0);
+    fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
+            memsz, memsz0);
+
+  bus.add_device(DEBUG_START, &debug_module);
 
   debug_mmu = new mmu_t(this, NULL);
 
-  for (size_t i = 0; i < procs.size(); i++)
-    procs[i] = new processor_t(isa, this, i);
+  for (size_t i = 0; i < procs.size(); i++) {
+    procs[i] = new processor_t(isa, this, i, halted);
+  }
 
   rtc.reset(new rtc_t(procs));
   make_config_string();
@@ -58,18 +61,33 @@ sim_t::~sim_t()
   free(mem);
 }
 
-int sim_t::run()
+void sim_thread_main(void* arg)
+{
+  ((sim_t*)arg)->main();
+}
+
+void sim_t::main()
 {
   if (!debug && log)
     set_procs_debug(true);
-  while (htif->tick())
+
+  while (!done())
   {
     if (debug || ctrlc_pressed)
       interactive();
     else
       step(INTERLEAVE);
+    if (remote_bitbang) {
+      remote_bitbang->tick();
+    }
   }
-  return htif->exit_code();
+}
+
+int sim_t::run()
+{
+  host = context_t::current();
+  target.init(sim_thread_main, this);
+  return htif_t::run();
 }
 
 void sim_t::step(size_t n)
@@ -89,19 +107,11 @@ void sim_t::step(size_t n)
         rtc->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
       }
 
-      htif->tick();
+      host->switch_to();
     }
   }
 }
 
-bool sim_t::running()
-{
-  for (size_t i = 0; i < procs.size(); i++)
-    if (procs[i]->running())
-      return true;
-  return false;
-}
-
 void sim_t::set_debug(bool value)
 {
   debug = value;
@@ -142,11 +152,13 @@ bool sim_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes)
 
 void sim_t::make_config_string()
 {
-  reg_t boot_rom_addr = DEFAULT_RSTVEC;
-  reg_t boot_rom_size = 0x2000;
-  reg_t rtc_addr = boot_rom_addr + boot_rom_size;
+  reg_t rtc_addr = EXT_IO_BASE;
   bus.add_device(rtc_addr, rtc.get());
 
+  const int align = 0x1000;
+  reg_t cpu_addr = rtc_addr + ((rtc->size() - 1) / align + 1) * align;
+  reg_t cpu_size = align;
+
   uint32_t reset_vec[8] = {
     0x297 + DRAM_BASE - DEFAULT_RSTVEC, // reset vector
     0x00028067,                         //   jump straight to DRAM_BASE
@@ -154,7 +166,7 @@ void sim_t::make_config_string()
     0,                                  // config string pointer
     0, 0, 0, 0                          // trap vector
   };
-  reset_vec[3] = boot_rom_addr + sizeof(reset_vec); // config string pointer
+  reset_vec[3] = DEFAULT_RSTVEC + sizeof(reset_vec); // config string pointer
 
   std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
 
@@ -180,16 +192,40 @@ void sim_t::make_config_string()
         "    " << "0 {\n" << // hart 0 on core i
         "      isa " << procs[i]->isa_string << ";\n"
         "      timecmp 0x" << (rtc_addr + 8*(1+i)) << ";\n"
+        "      ipi 0x" << cpu_addr << ";\n"
         "    };\n"
         "  };\n";
+    bus.add_device(cpu_addr, procs[i]);
+    cpu_addr += cpu_size;
   }
   s <<  "};\n";
 
   config_string = s.str();
   rom.insert(rom.end(), config_string.begin(), config_string.end());
-  assert(rom.size() < boot_rom_size);
-  rom.resize(boot_rom_size);
+  rom.resize((rom.size() / align + 1) * align);
 
   boot_rom.reset(new rom_device_t(rom));
-  bus.add_device(boot_rom_addr, boot_rom.get());
+  bus.add_device(DEFAULT_RSTVEC, boot_rom.get());
+}
+
+// htif
+
+void sim_t::idle()
+{
+  target.switch_to();
+}
+
+void sim_t::read_chunk(addr_t taddr, size_t len, void* dst)
+{
+  assert(len == 8);
+  auto data = debug_mmu->load_uint64(taddr);
+  memcpy(dst, &data, sizeof data);
+}
+
+void sim_t::write_chunk(addr_t taddr, size_t len, const void* src)
+{
+  assert(len == 8);
+  uint64_t data;
+  memcpy(&data, src, sizeof data);
+  debug_mmu->store_uint64(taddr, data);
 }