#include "sim.h"
#include "mmu.h"
-#include "gdbserver.h"
+#include "remote_bitbang.h"
#include <map>
#include <iostream>
#include <sstream>
sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
const std::vector<std::string>& args)
- : htif_t(args), procs(std::max(nprocs, size_t(1))),
- current_step(0), current_proc(0), debug(false), gdbserver(NULL)
+ : htif_t(args), debug_module(this), procs(std::max(nprocs, size_t(1))),
+ current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
{
signal(SIGINT, &handle_signal);
// allocate target machine's memory, shrinking it as necessary
size_t memsz0 = (size_t)mem_mb << 20;
size_t quantum = 1L << 20;
if (memsz0 == 0)
- memsz0 = (size_t)((sizeof(size_t) == 8 ? 4096 : 2048) - 256) << 20;
+ memsz0 = (size_t)2048 << 20;
memsz = memsz0;
while ((mem = (char*)calloc(1, memsz)) == NULL)
fprintf(stderr, "warning: only got %zu bytes of target mem (wanted %zu)\n",
memsz, memsz0);
- bus.add_device(DEBUG_START, &debug_module);
+ debug_module.add_device(&bus);
debug_mmu = new mmu_t(this, NULL);
interactive();
else
step(INTERLEAVE);
- if (gdbserver) {
- gdbserver->handle();
+ if (remote_bitbang) {
+ remote_bitbang->tick();
}
}
}
" riscv,isa = \"" << procs[i]->isa_string << "\";\n"
" mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
" clock-frequency = <" << CPU_HZ << ">;\n"
- " interrupt-controller;\n"
- " #interrupt-cells = <1>;\n"
+ " CPU" << i << "_intc: interrupt-controller {\n"
+ " #interrupt-cells = <1>;\n"
+ " interrupt-controller;\n"
+ " compatible = \"riscv,cpu-intc\";\n"
+ " };\n"
" };\n";
}
reg_t membs = DRAM_BASE;
" soc {\n"
" #address-cells = <2>;\n"
" #size-cells = <2>;\n"
- " compatible = \"ucbbar,spike-bare-soc\";\n"
+ " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
" ranges;\n"
" clint@" << CLINT_BASE << " {\n"
" compatible = \"riscv,clint0\";\n"
" interrupts-extended = <" << std::dec;
for (size_t i = 0; i < procs.size(); i++)
- s << "&CPU" << i << " 3 &CPU" << i << " 7 ";
+ s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
reg_t clintbs = CLINT_BASE;
reg_t clintsz = CLINT_SIZE;
s << std::hex << ">;\n"