check if register redirection is active, and if vectorisation enabled

[riscv-isa-sim.git] / riscv / sv.h

diff --git a/riscv/sv.h b/riscv/sv.h
index cd2f8fbb030384246701333719d4f82006a5987c..8c2bf3a4216fd6b1c0d483bda3b29bae12370203 100644 (file)
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -63,4 +63,6 @@ typedef struct {
 // 32 entries, only integer regs are predicates.
 extern sv_pred_entry sv_pred_tb[NXPR];
 
+bool sv_check_reg(bool intreg, uint64_t reg);
+
 #endif