[opcodes,pk,sim] add more vector traps (for #banks, illegal instructions)

[riscv-isa-sim.git] / riscv / trap.h

diff --git a/riscv/trap.h b/riscv/trap.h
index 698852c8b88c0410bdc3b8317c26f2ace6c499db..1a6db73bec38460a7a7034f77dda543290f80276 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -15,11 +15,11 @@
   DECLARE_TRAP(load_access_fault), \
   DECLARE_TRAP(store_access_fault), \
   DECLARE_TRAP(vector_disabled), \
+  DECLARE_TRAP(vector_bank), \
+  DECLARE_TRAP(vector_illegal_instruction), \
+  DECLARE_TRAP(reserved1), \
   DECLARE_TRAP(reserved2), \
   DECLARE_TRAP(reserved3), \
-  DECLARE_TRAP(reserved4), \
-  DECLARE_TRAP(reserved5), \
-  DECLARE_TRAP(reserved6), \
   DECLARE_TRAP(int0), \
   DECLARE_TRAP(int1), \
   DECLARE_TRAP(int2), \