[sim] vlen calc reflects the hardware

[riscv-isa-sim.git] / riscv / trap.h

diff --git a/riscv/trap.h b/riscv/trap.h
index 61b44360f6cb139828be09152d28ee0fecf593e6..1a6db73bec38460a7a7034f77dda543290f80276 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -10,15 +10,16 @@
   DECLARE_TRAP(interrupt), \
   DECLARE_TRAP(syscall), \
   DECLARE_TRAP(breakpoint), \
-  DECLARE_TRAP(data_address_misaligned), \
+  DECLARE_TRAP(load_address_misaligned), \
+  DECLARE_TRAP(store_address_misaligned), \
   DECLARE_TRAP(load_access_fault), \
   DECLARE_TRAP(store_access_fault), \
+  DECLARE_TRAP(vector_disabled), \
+  DECLARE_TRAP(vector_bank), \
+  DECLARE_TRAP(vector_illegal_instruction), \
   DECLARE_TRAP(reserved1), \
   DECLARE_TRAP(reserved2), \
   DECLARE_TRAP(reserved3), \
-  DECLARE_TRAP(reserved4), \
-  DECLARE_TRAP(reserved5), \
-  DECLARE_TRAP(reserved6), \
   DECLARE_TRAP(int0), \
   DECLARE_TRAP(int1), \
   DECLARE_TRAP(int2), \