bugfix in raising accelerator interrupts

[riscv-isa-sim.git] / riscv / trap.h

diff --git a/riscv/trap.h b/riscv/trap.h
index a7a823bcd3fc6479bfd9023dfb3ec99befaf56d0..8bc94f33c8b0575d36ec0b222278fb4c299490b1 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -5,7 +5,7 @@
 
 #include "decode.h"
 
-class state_t;
+struct state_t;
 
 class trap_t
 {
@@ -25,6 +25,7 @@ class mem_trap_t : public trap_t
   mem_trap_t(reg_t which, reg_t badvaddr)
     : trap_t(which), badvaddr(badvaddr) {}
   void side_effects(state_t* state);
+  reg_t get_badvaddr() { return badvaddr; }
  private:
   reg_t badvaddr;
 };
@@ -41,20 +42,16 @@ class mem_trap_t : public trap_t
   const char* name() { return "trap_"#x; } \
 };
 
-DECLARE_TRAP(0, instruction_address_misaligned)
-DECLARE_TRAP(1, instruction_access_fault)
-DECLARE_TRAP(2, illegal_instruction)
-DECLARE_TRAP(3, privileged_instruction)
-DECLARE_TRAP(4, fp_disabled)
-DECLARE_TRAP(5, reserved0)
-DECLARE_TRAP(6, syscall)
-DECLARE_TRAP(7, breakpoint)
-DECLARE_MEM_TRAP(8, load_address_misaligned)
-DECLARE_MEM_TRAP(9, store_address_misaligned)
-DECLARE_MEM_TRAP(10, load_access_fault)
-DECLARE_MEM_TRAP(11, store_access_fault)
-DECLARE_TRAP(12, vector_disabled)
-DECLARE_TRAP(13, vector_bank)
-DECLARE_TRAP(14, vector_illegal_instruction)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_FAULT_FETCH, instruction_access_fault)
+DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
+DECLARE_TRAP(CAUSE_SCALL, scall)
+DECLARE_TRAP(CAUSE_HCALL, hcall)
+DECLARE_TRAP(CAUSE_MCALL, mcall)
+DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
+DECLARE_MEM_TRAP(CAUSE_FAULT_LOAD, load_access_fault)
+DECLARE_MEM_TRAP(CAUSE_FAULT_STORE, store_access_fault)
 
 #endif