Don't take interrupts while in Debug Mode.

[riscv-isa-sim.git] / riscv / trap.h

diff --git a/riscv/trap.h b/riscv/trap.h
index a289a6842af5aff0c5782e175a7f6331eac33605..91e522396b42d9887372897ed19fe30252672c4a 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -46,8 +46,8 @@ class mem_trap_t : public trap_t
 
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
-DECLARE_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
-DECLARE_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_MEM_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
+DECLARE_MEM_TRAP(CAUSE_BREAKPOINT, breakpoint)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)