Rip out RVC for now

[riscv-isa-sim.git] / rvc / insns / c_fld.h

diff --git a/rvc/insns/c_fld.h b/rvc/insns/c_fld.h
new file mode 100644 (file)
index 0000000..a726039
--- /dev/null
+++ b/rvc/insns/c_fld.h
@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+FCRDS = mmu.load_int64(CRS1S+CIMM5*8);