[sim] renamed to riscv-isa-run

[riscv-isa-sim.git] / softfloat / f64_to_i32_r_minMag.c

diff --git a/softfloat/f64_to_i32_r_minMag.c b/softfloat/f64_to_i32_r_minMag.c
deleted file mode 100755 (executable)
index 39246c2..0000000
--- a/softfloat/f64_to_i32_r_minMag.c
+++ /dev/null
@@ -1,50 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast32_t f64_to_i32_r_minMag( float64_t a, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    bool sign;\r
-    int_fast16_t shiftCount;\r
-    uint_fast32_t absZ;\r
-    union { uint32_t ui; int32_t i; } uZ;\r
-    int_fast32_t z;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp < 0x3FF ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    sign = signF64UI( uiA );\r
-    if ( 0x41E < exp ) {\r
-        if ( ( exp == 0x7FF ) && sig ) sign = 0;\r
-        goto invalid;\r
-    }\r
-    sig |= UINT64_C( 0x0010000000000000 );\r
-    shiftCount = 0x433 - exp;\r
-    absZ = sig>>shiftCount;\r
-    uZ.ui = sign ? - absZ : absZ;\r
-    z = uZ.i;\r
-    if ( ( z < 0 ) != sign ) goto invalid;\r
-    if ( exact && ( (uint_fast64_t) absZ<<shiftCount != sig ) ) {\r
-        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-    }\r
-    return z;\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    return sign ? -0x7FFFFFFF - 1 : 0x7FFFFFFF;\r
-\r
-}\r
-\r