#include "ac_gpu_info.h"
#include "sid.h"
-#include "gfx9d.h"
+#include "util/macros.h"
#include "util/u_math.h"
#include <stdio.h>
case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
return 16;
default:
- fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
+ fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
assert(!"this should never occur");
return 2;
}
return value ? true : false;
}
-bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
+bool ac_query_gpu_info(int fd, void *dev_p,
struct radeon_info *info,
struct amdgpu_gpu_info *amdinfo)
{
+ struct drm_amdgpu_info_device device_info = {};
struct amdgpu_buffer_size_alignments alignment_info = {};
- struct amdgpu_heap_info vram, vram_vis, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
- struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
+ struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
struct amdgpu_gds_resource_info gds = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
int r, i, j;
+ amdgpu_device_handle dev = dev_p;
drmDevicePtr devinfo;
/* Get PCI info. */
info->pci_func = devinfo->businfo.pci->func;
drmFreeDevice(&devinfo);
+ assert(info->drm_major == 3);
+ info->is_amdgpu = true;
+
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(dev, amdinfo);
if (r) {
return false;
}
- r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
- if (r) {
- fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
- return false;
- }
-
- r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
- if (r) {
- fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
- return false;
- }
-
- r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
- AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
- &vram_vis);
+ r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
+ &device_info);
if (r) {
- fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
+ fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
return false;
}
- r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
+ r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
if (r) {
- fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
+ fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
return false;
}
return false;
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
}
}
- if (info->drm_major == 3 && info->drm_minor >= 17) {
+ if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
}
}
+ if (info->drm_minor >= 27) {
+ r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
+ return false;
+ }
+ }
+
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
&info->me_fw_version,
&info->me_fw_feature);
return false;
}
+ if (info->drm_minor >= 9) {
+ struct drm_amdgpu_memory_info meminfo = {};
+
+ r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
+ return false;
+ }
+
+ /* Note: usable_heap_size values can be random and can't be relied on. */
+ info->gart_size = meminfo.gtt.total_heap_size;
+ info->vram_size = meminfo.vram.total_heap_size;
+ info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
+ } else {
+ /* This is a deprecated interface, which reports usable sizes
+ * (total minus pinned), but the pinned size computation is
+ * buggy, so the values returned from these functions can be
+ * random.
+ */
+ struct amdgpu_heap_info vram, vram_vis, gtt;
+
+ r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
+ return false;
+ }
+
+ r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
+ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+ &vram_vis);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
+ return false;
+ }
+
+ r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
+ return false;
+ }
+
+ info->gart_size = gtt.heap_size;
+ info->vram_size = vram.heap_size;
+ info->vram_vis_size = vram_vis.heap_size;
+ }
+
/* Set chip identification. */
info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
info->vce_harvest_config = amdinfo->vce_harvest_config;
switch (info->pci_id) {
-#define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
+#define CHIPSET(pci_id, cfamily) \
+ case pci_id: \
+ info->family = CHIP_##cfamily; \
+ info->name = #cfamily; \
+ break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
return false;
}
- if (info->family >= CHIP_VEGA10)
+ /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */
+ if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) {
+ info->family = CHIP_RAVEN2;
+ info->name = "RAVEN2";
+ }
+
+ if (info->family >= CHIP_NAVI10)
+ info->chip_class = GFX10;
+ else if (info->family >= CHIP_VEGA10)
info->chip_class = GFX9;
else if (info->family >= CHIP_TONGA)
- info->chip_class = VI;
+ info->chip_class = GFX8;
else if (info->family >= CHIP_BONAIRE)
- info->chip_class = CIK;
+ info->chip_class = GFX7;
else if (info->family >= CHIP_TAHITI)
- info->chip_class = SI;
+ info->chip_class = GFX6;
else {
fprintf(stderr, "amdgpu: Unknown family.\n");
return false;
}
+ info->family_id = amdinfo->family_id;
+ info->chip_external_rev = amdinfo->chip_external_rev;
+ info->marketing_name = amdgpu_get_marketing_name(dev);
+ info->is_pro_graphics = info->marketing_name &&
+ (!strcmp(info->marketing_name, "Pro") ||
+ !strcmp(info->marketing_name, "PRO") ||
+ !strcmp(info->marketing_name, "Frontier"));
+
/* Set which chips have dedicated VRAM. */
info->has_dedicated_vram =
!(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
- /* Set hardware information. */
- info->gart_size = gtt.heap_size;
- info->vram_size = vram.heap_size;
- info->vram_vis_size = vram_vis.heap_size;
- info->gds_size = gds.gds_total_size;
- info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
/* The kernel can split large buffers in VRAM but not in GTT, so large
* allocations can fail or cause buffer movement failures in the kernel.
*/
- info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
+ if (info->has_dedicated_vram)
+ info->max_alloc_size = info->vram_size * 0.8;
+ else
+ info->max_alloc_size = info->gart_size * 0.7;
+
+ /* Set hardware information. */
+ info->gds_size = gds.gds_total_size;
+ info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
/* convert the shader clock from KHz to MHz */
info->max_shader_clock = amdinfo->max_engine_clk / 1000;
+ info->num_tcc_blocks = device_info.num_tcc_blocks;
info->max_se = amdinfo->num_shader_engines;
info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
info->has_hw_decode =
- (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
+ (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
+ (vcn_jpeg.available_rings != 0);
info->uvd_fw_version =
uvd.available_rings ? uvd_version : 0;
info->vce_fw_version =
info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
info->has_ctx_priority = info->drm_minor >= 22;
- /* TODO: Enable this once the kernel handles it efficiently. */
- info->has_local_buffers = info->drm_minor >= 20 &&
- !info->has_dedicated_vram;
+ info->has_local_buffers = info->drm_minor >= 20;
info->kernel_flushes_hdp_before_ib = true;
info->htile_cmask_support_1d_tiling = true;
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->has_bo_metadata = true;
info->has_gpu_reset_status_query = true;
- info->has_gpu_reset_counter_query = false;
info->has_eqaa_surface_allocator = true;
info->has_format_bc1_through_bc7 = true;
- /* DRM 3.1.0 doesn't flush TC for VI correctly. */
- info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
+ /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
+ info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
info->drm_minor >= 2;
info->has_indirect_compute_dispatch = true;
- /* SI doesn't support unaligned loads. */
- info->has_unaligned_shader_loads = info->chip_class != SI;
-
+ /* GFX6 doesn't support unaligned loads. */
+ info->has_unaligned_shader_loads = info->chip_class != GFX6;
+ /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
+ * these faults are mitigated in software.
+ * Disable sparse mappings on GFX9 due to hangs.
+ */
+ info->has_sparse_vm_mappings =
+ info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
+ info->drm_minor >= 13;
+ info->has_2d_tiling = true;
+ info->has_read_registers_query = true;
+ info->has_scheduled_fence_dependency = info->drm_minor >= 28;
+
+ info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
if (info->family == CHIP_KAVERI)
fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
info->clock_crystal_freq = 1;
}
- info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+ if (info->chip_class >= GFX10) {
+ info->tcc_cache_line_size = 128;
+ } else {
+ info->tcc_cache_line_size = 64;
+ }
info->gb_addr_config = amdinfo->gb_addr_cfg;
if (info->chip_class == GFX9) {
info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
+ info->has_graphics = gfx.available_rings > 0;
info->num_sdma_rings = util_bitcount(dma.available_rings);
info->num_compute_rings = util_bitcount(compute.available_rings);
+ /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
+ * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
+ * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
+ */
+ info->has_clear_state = info->chip_class >= GFX7;
+
+ info->has_distributed_tess = info->chip_class >= GFX8 &&
+ info->max_se >= 2;
+
+ info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR ||
+ info->chip_class >= GFX10;
+
+ info->has_rbplus = info->family == CHIP_STONEY ||
+ info->chip_class >= GFX9;
+
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
for (j = 0; j < info->max_sh_per_se; j++)
info->num_good_compute_units +=
util_bitcount(amdinfo->cu_bitmap[i][j]);
+ info->num_good_cu_per_sh = info->num_good_compute_units /
+ (info->max_se * info->max_sh_per_se);
memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
sizeof(amdinfo->gb_tile_mode));
info->pte_fragment_size = alignment_info.size_local;
info->gart_page_size = alignment_info.size_remote;
- if (info->chip_class == SI)
- info->gfx_ib_pad_with_type2 = TRUE;
+ if (info->chip_class == GFX6)
+ info->gfx_ib_pad_with_type2 = true;
unsigned ib_align = 0;
ib_align = MAX2(ib_align, gfx.ib_start_alignment);
ib_align = MAX2(ib_align, vce.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
- assert(ib_align);
+ ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
+ assert(ib_align);
info->ib_start_alignment = ib_align;
+ if (info->drm_minor >= 31 &&
+ (info->family == CHIP_RAVEN ||
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR)) {
+ if (info->num_render_backends == 1)
+ info->use_display_dcc_unaligned = true;
+ else
+ info->use_display_dcc_with_retile_blit = true;
+ }
+
+ info->has_gds_ordered_append = info->chip_class >= GFX7 &&
+ info->drm_minor >= 29;
return true;
}
printf(" pci_id = 0x%x\n", info->pci_id);
printf(" family = %i\n", info->family);
printf(" chip_class = %i\n", info->chip_class);
+ printf(" chip_external_rev = %i\n", info->chip_external_rev);
printf(" num_compute_rings = %u\n", info->num_compute_rings);
printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
+ printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
+ printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
+
printf("Memory info:\n");
printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
printf(" gart_page_size = %u\n", info->gart_page_size);
printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
- printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
+ printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
+ printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
+ printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
+ printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
+ printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);
printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
+ printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
+ printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
printf(" max_se = %i\n", info->max_se);
printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
printf("Render backend info:\n");
+ printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
printf(" num_render_backends = %i\n", info->num_render_backends);
printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
case CHIP_HAINAN:
case CHIP_KAVERI:
case CHIP_KABINI:
- case CHIP_MULLINS:
case CHIP_ICELAND:
case CHIP_CARRIZO:
case CHIP_STONEY:
void
ac_get_raster_config(struct radeon_info *info,
uint32_t *raster_config_p,
- uint32_t *raster_config_1_p)
+ uint32_t *raster_config_1_p,
+ uint32_t *se_tile_repeat_p)
{
- unsigned raster_config, raster_config_1;
+ unsigned raster_config, raster_config_1, se_tile_repeat;
switch (info->family) {
/* 1 SE / 1 RB */
case CHIP_HAINAN:
case CHIP_KABINI:
- case CHIP_MULLINS:
case CHIP_STONEY:
raster_config = 0x00000000;
raster_config_1 = 0x00000000;
/* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
* This decreases performance by up to 50% when the RB is the bottleneck.
*/
- if (info->family == CHIP_KAVERI && info->drm_major == 2)
+ if (info->family == CHIP_KAVERI && !info->is_amdgpu)
raster_config = 0x00000000;
/* Fiji: Old kernels have incorrect tiling config. This decreases
raster_config_1 = 0x0000002a;
}
+ unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
+ unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
+
+ /* I don't know how to calculate this, though this is probably a good guess. */
+ se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
+
*raster_config_p = raster_config;
*raster_config_1_p = raster_config_1;
+ if (se_tile_repeat_p)
+ *se_tile_repeat_p = se_tile_repeat;
}
void
assert(rb_per_pkr == 1 || rb_per_pkr == 2);
- if (info->chip_class >= CIK) {
+ if (info->chip_class >= GFX7) {
unsigned raster_config_1 = *cik_raster_config_1_p;
if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
(!se_mask[2] && !se_mask[3]))) {
}
}
}
+
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+ unsigned waves_per_threadgroup,
+ unsigned max_waves_per_sh,
+ unsigned threadgroups_per_cu)
+{
+ unsigned compute_resource_limits =
+ S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
+
+ if (info->chip_class >= GFX7) {
+ unsigned num_cu_per_se = info->num_good_compute_units /
+ info->max_se;
+
+ /* Force even distribution on all SIMDs in CU if the workgroup
+ * size is 64. This has shown some good improvements if # of CUs
+ * per SE is not a multiple of 4.
+ */
+ if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
+ compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
+
+ assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
+ compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
+ S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
+ } else {
+ /* GFX6 */
+ if (max_waves_per_sh) {
+ unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
+ compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
+ }
+ }
+ return compute_resource_limits;
+}
projects / mesa.git / blobdiff