ac: add has_rbplus to ac_gpu_info

[mesa.git] / src / amd / common / ac_gpu_info.c

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index a501d840b25986aa4d3b251520ea855e6bc6003f..50e92a405e336a38f2a626af646b3f1bb123ec08 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -26,6 +26,7 @@
 #include "ac_gpu_info.h"
 #include "sid.h"
 
+#include "util/macros.h"
 #include "util/u_math.h"
 
 #include <stdio.h>
@@ -436,9 +437,26 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
        assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
 
+       info->has_graphics = gfx.available_rings > 0;
        info->num_sdma_rings = util_bitcount(dma.available_rings);
        info->num_compute_rings = util_bitcount(compute.available_rings);
 
+       /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
+        * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
+        * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
+        */
+       info->has_clear_state = info->chip_class >= GFX7;
+
+       info->has_distributed_tess = info->chip_class >= GFX8 &&
+                                    info->max_se >= 2;
+
+       info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
+                                       info->family == CHIP_RENOIR ||
+                                       info->chip_class >= GFX10;
+
+       info->has_rbplus = info->family == CHIP_STONEY ||
+                          info->chip_class >= GFX9;
+
        /* Get the number of good compute units. */
        info->num_good_compute_units = 0;
        for (i = 0; i < info->max_se; i++)
@@ -459,7 +477,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        info->gart_page_size = alignment_info.size_remote;
 
        if (info->chip_class == GFX6)
-               info->gfx_ib_pad_with_type2 = TRUE;
+               info->gfx_ib_pad_with_type2 = true;
 
        unsigned ib_align = 0;
        ib_align = MAX2(ib_align, gfx.ib_start_alignment);
@@ -476,7 +494,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 
        if (info->drm_minor >= 31 &&
            (info->family == CHIP_RAVEN ||
-            info->family == CHIP_RAVEN2)) {
+            info->family == CHIP_RAVEN2 ||
+            info->family == CHIP_RENOIR)) {
                if (info->num_render_backends == 1)
                        info->use_display_dcc_unaligned = true;
                else
@@ -484,8 +503,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        }
 
        info->has_gds_ordered_append = info->chip_class >= GFX7 &&
-                                      info->drm_minor >= 29 &&
-                                      HAVE_LLVM >= 0x0800;
+                                      info->drm_minor >= 29;
        return true;
 }