info->num_sdma_rings = util_bitcount(dma.available_rings);
info->num_compute_rings = util_bitcount(compute.available_rings);
+ /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
+ * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
+ * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
+ */
+ info->has_clear_state = info->chip_class >= GFX7;
+
+ info->has_distributed_tess = info->chip_class >= GFX8 &&
+ info->max_se >= 2;
+
+ info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR ||
+ info->chip_class >= GFX10;
+
+ info->has_rbplus = info->family == CHIP_STONEY ||
+ info->chip_class >= GFX9;
+
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
if (info->drm_minor >= 31 &&
(info->family == CHIP_RAVEN ||
- info->family == CHIP_RAVEN2)) {
+ info->family == CHIP_RAVEN2 ||
+ info->family == CHIP_RENOIR)) {
if (info->num_render_backends == 1)
info->use_display_dcc_unaligned = true;
else
}
info->has_gds_ordered_append = info->chip_class >= GFX7 &&
- info->drm_minor >= 29 &&
- HAVE_LLVM >= 0x0800;
+ info->drm_minor >= 29;
return true;
}