ac: add has_rbplus to ac_gpu_info

[mesa.git] / src / amd / common / ac_gpu_info.c

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index c51a442b540f81628527af62432ee1bea72f1afe..50e92a405e336a38f2a626af646b3f1bb123ec08 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -26,6 +26,7 @@
 #include "ac_gpu_info.h"
 #include "sid.h"
 
+#include "util/macros.h"
 #include "util/u_math.h"
 
 #include <stdio.h>
@@ -323,7 +324,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                info->name = "RAVEN2";
        }
 
-       if (info->family >= CHIP_VEGA10)
+       if (info->family >= CHIP_NAVI10)
+               info->chip_class = GFX10;
+       else if (info->family >= CHIP_VEGA10)
                info->chip_class = GFX9;
        else if (info->family >= CHIP_TONGA)
                info->chip_class = GFX8;
@@ -403,6 +406,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        info->has_read_registers_query = true;
        info->has_scheduled_fence_dependency = info->drm_minor >= 28;
 
+       info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
        info->num_render_backends = amdinfo->rb_pipes;
        /* The value returned by the kernel driver was wrong. */
        if (info->family == CHIP_KAVERI)
@@ -413,7 +417,11 @@ bool ac_query_gpu_info(int fd, void *dev_p,
                fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
                info->clock_crystal_freq = 1;
        }
-       info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
+       if (info->chip_class >= GFX10) {
+               info->tcc_cache_line_size = 128;
+       } else {
+               info->tcc_cache_line_size = 64;
+       }
        info->gb_addr_config = amdinfo->gb_addr_cfg;
        if (info->chip_class == GFX9) {
                info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
@@ -429,9 +437,26 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
        assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
 
+       info->has_graphics = gfx.available_rings > 0;
        info->num_sdma_rings = util_bitcount(dma.available_rings);
        info->num_compute_rings = util_bitcount(compute.available_rings);
 
+       /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
+        * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
+        * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
+        */
+       info->has_clear_state = info->chip_class >= GFX7;
+
+       info->has_distributed_tess = info->chip_class >= GFX8 &&
+                                    info->max_se >= 2;
+
+       info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
+                                       info->family == CHIP_RENOIR ||
+                                       info->chip_class >= GFX10;
+
+       info->has_rbplus = info->family == CHIP_STONEY ||
+                          info->chip_class >= GFX9;
+
        /* Get the number of good compute units. */
        info->num_good_compute_units = 0;
        for (i = 0; i < info->max_se; i++)
@@ -452,7 +477,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        info->gart_page_size = alignment_info.size_remote;
 
        if (info->chip_class == GFX6)
-               info->gfx_ib_pad_with_type2 = TRUE;
+               info->gfx_ib_pad_with_type2 = true;
 
        unsigned ib_align = 0;
        ib_align = MAX2(ib_align, gfx.ib_start_alignment);
@@ -469,7 +494,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 
        if (info->drm_minor >= 31 &&
            (info->family == CHIP_RAVEN ||
-            info->family == CHIP_RAVEN2)) {
+            info->family == CHIP_RAVEN2 ||
+            info->family == CHIP_RENOIR)) {
                if (info->num_render_backends == 1)
                        info->use_display_dcc_unaligned = true;
                else
@@ -477,8 +503,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        }
 
        info->has_gds_ordered_append = info->chip_class >= GFX7 &&
-                                      info->drm_minor >= 29 &&
-                                      HAVE_LLVM >= 0x0800;
+                                      info->drm_minor >= 29;
        return true;
 }
 
@@ -519,6 +544,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    pci_id = 0x%x\n", info->pci_id);
        printf("    family = %i\n", info->family);
        printf("    chip_class = %i\n", info->chip_class);
+       printf("    chip_external_rev = %i\n", info->chip_external_rev);
        printf("    num_compute_rings = %u\n", info->num_compute_rings);
        printf("    num_sdma_rings = %i\n", info->num_sdma_rings);
        printf("    clock_crystal_freq = %i\n", info->clock_crystal_freq);
@@ -592,6 +618,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 
        printf("Render backend info:\n");
+       printf("    pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
        printf("    num_render_backends = %i\n", info->num_render_backends);
        printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
        printf("    pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
@@ -886,3 +913,35 @@ ac_get_harvested_configs(struct radeon_info *info,
                }
        }
 }
+
+unsigned ac_get_compute_resource_limits(struct radeon_info *info,
+                                       unsigned waves_per_threadgroup,
+                                       unsigned max_waves_per_sh,
+                                       unsigned threadgroups_per_cu)
+{
+       unsigned compute_resource_limits =
+               S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
+
+       if (info->chip_class >= GFX7) {
+               unsigned num_cu_per_se = info->num_good_compute_units /
+                                        info->max_se;
+
+               /* Force even distribution on all SIMDs in CU if the workgroup
+                * size is 64. This has shown some good improvements if # of CUs
+                * per SE is not a multiple of 4.
+                */
+               if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
+                       compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
+
+               assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
+               compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
+                                          S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
+       } else {
+               /* GFX6 */
+               if (max_waves_per_sh) {
+                       unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
+                       compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
+               }
+       }
+       return compute_resource_limits;
+}