radv,aco: report ACO errors/warnings back via VK_EXT_debug_report
[mesa.git] / src / amd / vulkan / radv_cs.h
index 16649c55e6ae906874584e36e172e93e0f3b97fb..2bef75c80ad86cc730ffc5befa6f007af69dccef 100644 (file)
@@ -82,6 +82,18 @@ static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs,
        radeon_emit(cs, value);
 }
 
+static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs,
+                                             unsigned reg, unsigned value,
+                                             unsigned mask)
+{
+       assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
+       assert(cs->cdw + 4 <= cs->max_dw);
+       radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0));
+       radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
+       radeon_emit(cs, mask);
+       radeon_emit(cs, value);
+}
+
 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
 {
        assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
@@ -149,4 +161,20 @@ static inline void radeon_set_uconfig_reg_idx(const struct radv_physical_device
        radeon_emit(cs, value);
 }
 
+static inline void radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs,
+                                                   unsigned reg,
+                                                   unsigned value)
+{
+       assert(reg < CIK_UCONFIG_REG_OFFSET);
+       assert(cs->cdw + 6 <= cs->max_dw);
+
+       radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+       radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
+                       COPY_DATA_DST_SEL(COPY_DATA_PERF));
+       radeon_emit(cs, value);
+       radeon_emit(cs, 0); /* unused */
+       radeon_emit(cs, reg >> 2);
+       radeon_emit(cs, 0); /* unused */
+}
+
 #endif /* RADV_CS_H */