ac: add has_rbplus to ac_gpu_info

[mesa.git] / src / amd / vulkan / radv_pipeline.c

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 2fdf241cb667bfbfabaf7bf4a4e02ae2c4ccda67..97ab503bef31d49c1bb7d8982d915458cfc191bb 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -865,7 +865,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
                blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
        }
 
-       if (pipeline->device->physical_device->has_rbplus) {
+       if (pipeline->device->physical_device->rad_info.has_rbplus) {
                /* Disable RB+ blend optimizations for dual source blending. */
                if (blend.mrt0_is_dual_src) {
                        for (i = 0; i < 8; i++) {
@@ -2010,7 +2010,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
        else
                topology = V_028B6C_OUTPUT_TRIANGLE_CW;
 
-       if (pipeline->device->has_distributed_tess) {
+       if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
                if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
                    pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
                        distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
@@ -2320,6 +2320,7 @@ radv_fill_shader_keys(struct radv_device *device,
        }
 
        if (device->physical_device->rad_info.chip_class >= GFX10 &&
+           device->physical_device->rad_info.family != CHIP_NAVI14 &&
            !(device->instance->debug_flags & RADV_DEBUG_NO_NGG)) {
                if (nir[MESA_SHADER_TESS_CTRL]) {
                        keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
@@ -3328,7 +3329,7 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
        radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
        radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
 
-       if (pipeline->device->physical_device->has_rbplus) {
+       if (pipeline->device->physical_device->rad_info.has_rbplus) {
 
                radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
                radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
@@ -4053,7 +4054,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
        else
                z_order = V_02880C_LATE_Z;
 
-       bool disable_rbplus = device->physical_device->has_rbplus &&
+       bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
                              !device->physical_device->rbplus_allowed;
 
        /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
@@ -4377,7 +4378,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
                    radv_pipeline_has_gs(pipeline))
                        ia_multi_vgt_param.partial_vs_wave = true;
                /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
-               if (device->has_distributed_tess) {
+               if (device->physical_device->rad_info.has_distributed_tess) {
                        if (radv_pipeline_has_gs(pipeline)) {
                                if (device->physical_device->rad_info.chip_class <= GFX8)
                                        ia_multi_vgt_param.partial_es_wave = true;