radv/meta: fix blit paths for depth/stencil (v2.1)

[mesa.git] / src / amd / vulkan / radv_private.h

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index a416f38a7303c1ec4a18a3230ea4399a3935af91..acc4ed4dc92257a6292f25115af0f42d2d14519e 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -106,11 +106,6 @@ enum radv_mem_type {
        RADV_MEM_TYPE_COUNT
 };
 
-enum radv_mem_flags_bits {
-       /* enable implicit synchronization when accessing the underlying bo */
-       RADV_MEM_IMPLICIT_SYNC = 1 << 0,
-};
-
 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 
 static inline uint32_t
@@ -266,7 +261,7 @@ struct radv_physical_device {
        struct radeon_winsys *ws;
        struct radeon_info rad_info;
        char                                        path[20];
-       const char *                                name;
+       char                                        name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
        uint8_t                                     driver_uuid[VK_UUID_SIZE];
        uint8_t                                     device_uuid[VK_UUID_SIZE];
        uint8_t                                     cache_uuid[VK_UUID_SIZE];
@@ -358,6 +353,22 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device,
                                   const void *const *codes,
                                   const unsigned *code_sizes);
 
+enum radv_blit_ds_layout {
+       RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
+       RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
+       RADV_BLIT_DS_LAYOUT_COUNT,
+};
+
+static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
+{
+       return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
+}
+
+static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
+{
+       return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
+}
+
 struct radv_meta_state {
        VkAllocationCallbacks alloc;
 
@@ -390,12 +401,12 @@ struct radv_meta_state {
                /** Pipeline that blits from a 3D image. */
                VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 
-               VkRenderPass depth_only_rp;
+               VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
                VkPipeline depth_only_1d_pipeline;
                VkPipeline depth_only_2d_pipeline;
                VkPipeline depth_only_3d_pipeline;
 
-               VkRenderPass stencil_only_rp;
+               VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
                VkPipeline stencil_only_1d_pipeline;
                VkPipeline stencil_only_2d_pipeline;
                VkPipeline stencil_only_3d_pipeline;
@@ -406,21 +417,22 @@ struct radv_meta_state {
        struct {
                VkRenderPass render_passes[NUM_META_FS_KEYS];
 
-               VkPipelineLayout p_layouts[2];
-               VkDescriptorSetLayout ds_layouts[2];
-               VkPipeline pipelines[2][NUM_META_FS_KEYS];
+               VkPipelineLayout p_layouts[3];
+               VkDescriptorSetLayout ds_layouts[3];
+               VkPipeline pipelines[3][NUM_META_FS_KEYS];
 
-               VkRenderPass depth_only_rp;
-               VkPipeline depth_only_pipeline[2];
+               VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+               VkPipeline depth_only_pipeline[3];
 
-               VkRenderPass stencil_only_rp;
-               VkPipeline stencil_only_pipeline[2];
+               VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
+               VkPipeline stencil_only_pipeline[3];
        } blit2d;
 
        struct {
                VkPipelineLayout                          img_p_layout;
                VkDescriptorSetLayout                     img_ds_layout;
                VkPipeline pipeline;
+               VkPipeline pipeline_3d;
        } itob;
        struct {
                VkPipelineLayout                          img_p_layout;
@@ -439,6 +451,7 @@ struct radv_meta_state {
        } cleari;
 
        struct {
+               VkPipelineLayout                          p_layout;
                VkPipeline                                pipeline;
                VkRenderPass                              pass;
        } resolve;
@@ -464,12 +477,14 @@ struct radv_meta_state {
        } resolve_fragment;
 
        struct {
+               VkPipelineLayout                          p_layout;
                VkPipeline                                decompress_pipeline;
                VkPipeline                                resummarize_pipeline;
                VkRenderPass                              pass;
        } depth_decomp[1 + MAX_SAMPLES_LOG2];
 
        struct {
+               VkPipelineLayout                          p_layout;
                VkPipeline                                cmask_eliminate_pipeline;
                VkPipeline                                fmask_decompress_pipeline;
                VkRenderPass                              pass;
@@ -547,6 +562,7 @@ struct radv_device {
        bool dfsm_allowed;
        uint32_t tess_offchip_block_dw_size;
        uint32_t scratch_waves;
+       uint32_t dispatch_initiator;
 
        uint32_t gs_table_depth;
 
@@ -701,6 +717,7 @@ enum radv_cmd_dirty_bits {
        RADV_CMD_DIRTY_PIPELINE                          = 1 << 9,
        RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 10,
        RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 11,
+       RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 12,
 };
 
 enum radv_cmd_flush_bits {
@@ -809,7 +826,6 @@ struct radv_attachment_state {
 
 struct radv_cmd_state {
        /* Vertex descriptors */
-       bool                                          vb_dirty;
        bool                                          vb_prefetch_dirty;
        uint64_t                                      vb_va;
        unsigned                                      vb_size;
@@ -835,6 +851,7 @@ struct radv_cmd_state {
        uint32_t                                     index_type;
        uint32_t                                     max_index_count;
        uint64_t                                     index_va;
+       int32_t                                      last_index_type;
 
        int32_t                                      last_primitive_reset_en;
        uint32_t                                     last_primitive_reset_index;
@@ -862,6 +879,14 @@ struct radv_cmd_buffer_upload {
        struct list_head list;
 };
 
+enum radv_cmd_buffer_status {
+       RADV_CMD_BUFFER_STATUS_INVALID,
+       RADV_CMD_BUFFER_STATUS_INITIAL,
+       RADV_CMD_BUFFER_STATUS_RECORDING,
+       RADV_CMD_BUFFER_STATUS_EXECUTABLE,
+       RADV_CMD_BUFFER_STATUS_PENDING,
+};
+
 struct radv_cmd_buffer {
        VK_LOADER_DATA                               _loader_data;
 
@@ -872,6 +897,7 @@ struct radv_cmd_buffer {
 
        VkCommandBufferUsageFlags                    usage_flags;
        VkCommandBufferLevel                         level;
+       enum radv_cmd_buffer_status status;
        struct radeon_winsys_cs *cs;
        struct radv_cmd_state state;
        struct radv_vertex_binding                   vertex_bindings[MAX_VBS];
@@ -988,11 +1014,6 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
 bool radv_get_memory_fd(struct radv_device *device,
                        struct radv_device_memory *memory,
                        int *pFD);
-VkResult radv_alloc_memory(VkDevice _device,
-                          const VkMemoryAllocateInfo* pAllocateInfo,
-                          const VkAllocationCallbacks* pAllocator,
-                          enum radv_mem_flags_bits flags,
-                          VkDeviceMemory* pMem);
 
 /*
  * Takes x,y,z as exact numbers of invocations, instead of blocks.
@@ -1255,7 +1276,6 @@ struct radv_cmask_info {
        uint64_t size;
        unsigned alignment;
        unsigned slice_tile_max;
-       unsigned base_address_reg;
 };
 
 struct radv_image {
@@ -1360,14 +1380,12 @@ struct radv_image_view {
        uint32_t level_count;
        VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
 
-       uint32_t descriptor[8];
-       uint32_t fmask_descriptor[8];
+       uint32_t descriptor[16];
 
        /* Descriptor for use as a storage image as opposed to a sampled image.
         * This has a few differences for cube maps (e.g. type).
         */
-       uint32_t storage_descriptor[8];
-       uint32_t storage_fmask_descriptor[8];
+       uint32_t storage_descriptor[16];
 };
 
 struct radv_image_create_info {
@@ -1457,8 +1475,6 @@ struct radv_color_buffer_info {
        uint32_t cb_color_fmask_slice;
        uint32_t cb_clear_value0;
        uint32_t cb_clear_value1;
-       uint32_t micro_tile_mode;
-       uint32_t gfx9_epitch;
 };
 
 struct radv_ds_buffer_info {
@@ -1561,7 +1577,8 @@ VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
                             int num_wait_sems,
                             const VkSemaphore *wait_sems,
                             int num_signal_sems,
-                            const VkSemaphore *signal_sems);
+                            const VkSemaphore *signal_sems,
+                            VkFence fence);
 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
 
 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
@@ -1600,6 +1617,9 @@ struct radv_fence {
        struct radeon_winsys_fence *fence;
        bool submitted;
        bool signalled;
+
+       uint32_t syncobj;
+       uint32_t temp_syncobj;
 };
 
 struct radeon_winsys_sem;