* IN THE SOFTWARE.
*/
-/* command buffer handling for SI */
+/* command buffer handling for AMD GCN */
#include "radv_private.h"
#include "radv_shader.h"
#include "radv_cs.h"
#include "sid.h"
-#include "gfx9d.h"
#include "radv_util.h"
#include "main/macros.h"
raster_config_se);
for (se = 0; se < num_se; se++) {
- /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
- if (physical_device->rad_info.chip_class < CIK)
+ /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
+ if (physical_device->rad_info.chip_class < GFX7)
radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
S_00802C_SE_INDEX(se) |
S_00802C_SH_BROADCAST_WRITES(1) |
radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
}
- /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
- if (physical_device->rad_info.chip_class < CIK)
+ /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
+ if (physical_device->rad_info.chip_class < GFX7)
radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX,
S_00802C_SE_BROADCAST_WRITES(1) |
S_00802C_SH_BROADCAST_WRITES(1) |
S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
- if (physical_device->rad_info.chip_class >= CIK)
+ if (physical_device->rad_info.chip_class >= GFX7)
radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
}
-static void
+void
si_emit_compute(struct radv_physical_device *physical_device,
struct radeon_cmdbuf *cs)
{
radeon_emit(cs, 0);
radeon_emit(cs, 0);
- radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
- S_00B854_WAVES_PER_SH(0x3));
- radeon_emit(cs, 0);
- /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
+ radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
+ /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
+ * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
+ radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
- radeon_emit(cs, S_00B85C_SH0_CU_EN(0xffff) | S_00B85C_SH1_CU_EN(0xffff));
- if (physical_device->rad_info.chip_class >= CIK) {
+ if (physical_device->rad_info.chip_class >= GFX7) {
/* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
radeon_set_sh_reg_seq(cs,
R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
- radeon_emit(cs, S_00B864_SH0_CU_EN(0xffff) |
- S_00B864_SH1_CU_EN(0xffff));
- radeon_emit(cs, S_00B868_SH0_CU_EN(0xffff) |
- S_00B868_SH1_CU_EN(0xffff));
+ radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
+ S_00B858_SH1_CU_EN(0xffff));
+ radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) |
+ S_00B858_SH1_CU_EN(0xffff));
}
+ if (physical_device->rad_info.chip_class >= GFX10)
+ radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
+
/* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
* and is now per pipe, so it should be handled in the
* kernel if we want to use something other than the default value,
* which is now 0x22f.
*/
- if (physical_device->rad_info.chip_class <= SI) {
+ if (physical_device->rad_info.chip_class <= GFX6) {
/* XXX: This should be:
* (number of compute units) * 4 * (waves per simd) - 1 */
}
}
-void
-si_init_compute(struct radv_cmd_buffer *cmd_buffer)
-{
- struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
- si_emit_compute(physical_device, cmd_buffer->cs);
-}
-
/* 12.4 fixed-point */
static unsigned radv_pack_float_12p4(float x)
{
ac_get_raster_config(&physical_device->rad_info,
&raster_config,
- &raster_config_1);
+ &raster_config_1, NULL);
/* Always use the default config when all backends are enabled
* (or when we failed to determine the enabled backends).
if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG,
raster_config);
- if (physical_device->rad_info.chip_class >= CIK)
+ if (physical_device->rad_info.chip_class >= GFX7)
radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1,
raster_config_1);
} else {
}
}
-static void
-si_emit_config(struct radv_physical_device *physical_device,
- struct radeon_cmdbuf *cs)
+void
+si_emit_graphics(struct radv_physical_device *physical_device,
+ struct radeon_cmdbuf *cs)
{
int i;
- /* Only SI can disable CLEAR_STATE for now. */
+ /* Only GFX6 can disable CLEAR_STATE for now. */
assert(physical_device->has_clear_state ||
- physical_device->rad_info.chip_class == SI);
+ physical_device->rad_info.chip_class == GFX6);
radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
radeon_emit(cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
radeon_emit(cs, 0);
}
- if (physical_device->rad_info.chip_class <= VI)
+ if (physical_device->rad_info.chip_class <= GFX8)
si_set_raster_config(physical_device, cs);
radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
/* FIXME calculate these values somehow ??? */
- if (physical_device->rad_info.chip_class <= VI) {
+ if (physical_device->rad_info.chip_class <= GFX8) {
radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
}
radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
if (!physical_device->has_clear_state)
radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
- if (physical_device->rad_info.chip_class < CIK)
+ if (physical_device->rad_info.chip_class < GFX7)
radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
S_008A14_CLIP_VTX_REORDER_ENA(1));
- radeon_set_context_reg(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
- radeon_set_context_reg(cs, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
-
if (!physical_device->has_clear_state)
radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
/* CLEAR_STATE doesn't clear these correctly on certain generations.
* I don't know why. Deduced by trial and error.
*/
- if (physical_device->rad_info.chip_class <= CIK) {
+ if (physical_device->rad_info.chip_class <= GFX7) {
radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
S_028204_WINDOW_OFFSET_DISABLE(1));
if (!physical_device->has_clear_state) {
radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
- /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
+ /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
- if (physical_device->rad_info.chip_class >= GFX9) {
+ if (physical_device->rad_info.chip_class >= GFX10) {
+ radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
+ radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
+ radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
+ } else if (physical_device->rad_info.chip_class >= GFX9) {
radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
}
- if (physical_device->rad_info.chip_class >= CIK) {
+ if (physical_device->rad_info.chip_class >= GFX7) {
+ if (physical_device->rad_info.chip_class >= GFX10) {
+ /* Logical CUs 16 - 31 */
+ radeon_set_sh_reg(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
+ S_00B404_CU_EN(0xffff));
+ radeon_set_sh_reg(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
+ S_00B204_CU_EN(0xffff) |
+ S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
+ radeon_set_sh_reg(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
+ S_00B104_CU_EN(0xffff));
+ radeon_set_sh_reg(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
+ S_00B004_CU_EN(0xffff));
+ }
+
if (physical_device->rad_info.chip_class >= GFX9) {
radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
- if (physical_device->rad_info.num_good_compute_units /
- (physical_device->rad_info.max_se * physical_device->rad_info.max_sh_per_se) <= 4) {
+ if (physical_device->rad_info.num_good_cu_per_sh <= 4) {
/* Too few available compute units per SH. Disallowing
* VS to run on CU0 could hurt us more than late VS
* allocation would help.
S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
}
- if (physical_device->rad_info.chip_class >= VI) {
+ if (physical_device->rad_info.chip_class >= GFX10) {
+ radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
+ radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
+ physical_device->rad_info.pa_sc_tile_steering_override);
+ radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
+ S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+ S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+ S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+ S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
+ S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
+ S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
+ S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
+
+ radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
+ S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+ S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+ S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+ S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
+ S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
+ S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
+ S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
+ S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
+ }
+
+ if (physical_device->rad_info.chip_class >= GFX8) {
uint32_t vgt_tess_distribution;
- radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
- S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
- S_028424_OVERWRITE_COMBINER_WATERMARK(4));
vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) |
S_028B50_ACCUM_TRI(11) |
if (physical_device->rad_info.chip_class >= GFX9) {
unsigned num_se = physical_device->rad_info.max_se;
unsigned pc_lines = 0;
+ unsigned max_alloc_count = 0;
switch (physical_device->rad_info.family) {
case CHIP_VEGA10:
case CHIP_VEGA12:
+ case CHIP_VEGA20:
pc_lines = 4096;
break;
case CHIP_RAVEN:
+ case CHIP_RAVEN2:
+ case CHIP_NAVI10:
+ case CHIP_NAVI12:
pc_lines = 1024;
break;
+ case CHIP_NAVI14:
+ pc_lines = 512;
+ break;
default:
assert(0);
}
+ if (physical_device->rad_info.chip_class >= GFX10) {
+ max_alloc_count = pc_lines / 3;
+ } else {
+ max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
+ }
+
radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
- S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
+ S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
S_028C48_MAX_PRIM_PER_BATCH(1023));
radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
si_emit_compute(physical_device, cs);
}
-void si_init_config(struct radv_cmd_buffer *cmd_buffer)
-{
- struct radv_physical_device *physical_device = cmd_buffer->device->physical_device;
-
- si_emit_config(physical_device, cmd_buffer->cs);
-}
-
void
cik_create_gfx_config(struct radv_device *device)
{
if (!cs)
return;
- si_emit_config(device->physical_device, cs);
+ si_emit_graphics(device->physical_device, cs);
while (cs->cdw & 7) {
if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
RADEON_DOMAIN_GTT,
RADEON_FLAG_CPU_ACCESS|
RADEON_FLAG_NO_INTERPROCESS_SHARING |
- RADEON_FLAG_READ_ONLY);
+ RADEON_FLAG_READ_ONLY,
+ RADV_BO_PRIORITY_CS);
if (!device->gfx_init)
goto fail;
VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
get_viewport_xform(viewports + i, scale, translate);
- scale[0] = abs(scale[0]);
- scale[1] = abs(scale[1]);
+ scale[0] = fabsf(scale[0]);
+ scale[1] = fabsf(scale[1]);
if (scale[0] < 0.5)
scale[0] = 0.5;
if (scale[1] < 0.5)
scale[1] = 0.5;
- guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
- guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
+ guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
+ guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
S_028250_TL_Y(scissor.offset.y) |
uint32_t
si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
bool instanced_draw, bool indirect_draw,
+ bool count_from_stream_output,
uint32_t draw_vertex_count)
{
enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
ia_switch_on_eoi = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.ia_switch_on_eoi;
partial_vs_wave = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.partial_vs_wave;
- if (chip_class >= CIK) {
+ if (chip_class >= GFX7) {
wd_switch_on_eop = cmd_buffer->state.pipeline->graphics.ia_multi_vgt_param.wd_switch_on_eop;
/* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
* Assume indirect draws always use small instances.
* This is needed for good VS wave utilization.
*/
- if (chip_class <= VI &&
+ if (chip_class <= GFX8 &&
info->max_se == 4 &&
multi_instances_smaller_than_primgroup)
wd_switch_on_eop = true;
- /* Required on CIK and later. */
+ /* Required on GFX7 and later. */
if (info->max_se > 2 && !wd_switch_on_eop)
ia_switch_on_eoi = true;
- /* Required by Hawaii and, for some special cases, by VI. */
+ /* Required by Hawaii and, for some special cases, by GFX8. */
if (ia_switch_on_eoi &&
(family == CHIP_HAWAII ||
- (chip_class == VI &&
+ (chip_class == GFX8 &&
/* max primgroup in wave is always 2 - leave this for documentation */
(radv_pipeline_has_gs(cmd_buffer->state.pipeline) || max_primgroup_in_wave != 2))))
partial_vs_wave = true;
(instanced_draw || indirect_draw))
partial_vs_wave = true;
+ /* Hardware requirement when drawing primitives from a stream
+ * output buffer.
+ */
+ if (count_from_stream_output)
+ wd_switch_on_eop = true;
+
/* If the WD switch is false, the IA switch must be false too. */
assert(wd_switch_on_eop || !ia_switch_on_eop);
}
/* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
- if (chip_class <= VI && ia_switch_on_eoi)
+ if (chip_class <= GFX8 && ia_switch_on_eoi)
partial_es_wave = true;
if (radv_pipeline_has_gs(cmd_buffer->state.pipeline)) {
S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
- S_028AA8_WD_SWITCH_ON_EOP(chip_class >= CIK ? wd_switch_on_eop : 0);
+ S_028AA8_WD_SWITCH_ON_EOP(chip_class >= GFX7 ? wd_switch_on_eop : 0);
}
unsigned event, unsigned event_flags,
unsigned data_sel,
uint64_t va,
- uint32_t old_fence,
uint32_t new_fence,
uint64_t gfx9_eop_bug_va)
{
* counters) must immediately precede every timestamp event to
* prevent a GPU hang on GFX9.
*/
- if (chip_class == GFX9) {
+ if (chip_class == GFX9 && !is_mec) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
radeon_emit(cs, gfx9_eop_bug_va);
if (!is_gfx8_mec)
radeon_emit(cs, 0); /* unused */
} else {
- if (chip_class == CIK ||
- chip_class == VI) {
+ if (chip_class == GFX7 ||
+ chip_class == GFX8) {
/* Two EOP events are required to make all engines go idle
* (and optional cache flushes executed) before the timestamp
* is written.
radeon_emit(cs, op);
radeon_emit(cs, va);
radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
- radeon_emit(cs, old_fence); /* immediate data */
+ radeon_emit(cs, 0); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
}
void
-si_emit_wait_fence(struct radeon_cmdbuf *cs,
- uint64_t va, uint32_t ref,
- uint32_t mask)
+radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va,
+ uint32_t ref, uint32_t mask)
{
+ assert(op == WAIT_REG_MEM_EQUAL ||
+ op == WAIT_REG_MEM_NOT_EQUAL ||
+ op == WAIT_REG_MEM_GREATER_OR_EQUAL);
+
radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, false));
- radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
+ radeon_emit(cs, op | WAIT_REG_MEM_MEM_SPACE(1));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, ref); /* reference value */
if (flush_bits & RADV_CMD_FLAG_INV_ICACHE)
cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
- if (flush_bits & RADV_CMD_FLAG_INV_SMEM_L1)
+ if (flush_bits & RADV_CMD_FLAG_INV_SCACHE)
cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
- if (chip_class <= VI) {
+ if (chip_class <= GFX8) {
if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
S_0085F0_CB0_DEST_BASE_ENA(1) |
S_0085F0_CB7_DEST_BASE_ENA(1);
/* Necessary for DCC */
- if (chip_class >= VI) {
+ if (chip_class >= GFX8) {
si_cs_emit_write_event_eop(cs,
chip_class,
is_mec,
V_028A90_FLUSH_AND_INV_CB_DATA_TS,
0,
EOP_DATA_SEL_DISCARD,
- 0, 0, 0,
+ 0, 0,
gfx9_eop_bug_va);
}
}
EVENT_TC_MD_ACTION_ENA;
/* Ideally flush TC together with CB/DB. */
- if (flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) {
+ if (flush_bits & RADV_CMD_FLAG_INV_L2) {
/* Writeback and invalidate everything in L2 & L1. */
tc_flags = EVENT_TC_ACTION_ENA |
EVENT_TC_WB_ACTION_ENA;
/* Clear the flags. */
- flush_bits &= ~(RADV_CMD_FLAG_INV_GLOBAL_L2 |
- RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 |
- RADV_CMD_FLAG_INV_VMEM_L1);
+ flush_bits &= ~(RADV_CMD_FLAG_INV_L2 |
+ RADV_CMD_FLAG_WB_L2 |
+ RADV_CMD_FLAG_INV_VCACHE);
}
assert(flush_cnt);
- uint32_t old_fence = (*flush_cnt)++;
+ (*flush_cnt)++;
si_cs_emit_write_event_eop(cs, chip_class, false, cb_db_event, tc_flags,
EOP_DATA_SEL_VALUE_32BIT,
- flush_va, old_fence, *flush_cnt,
+ flush_va, *flush_cnt,
gfx9_eop_bug_va);
- si_emit_wait_fence(cs, flush_va, *flush_cnt, 0xffffffff);
+ radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, flush_va,
+ *flush_cnt, 0xffffffff);
}
/* VGT state sync */
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
}
+ /* VGT streamout state sync */
+ if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
+ }
+
/* Make sure ME is idle (it executes most packets) before continuing.
* This prevents read-after-write hazards between PFP and ME.
*/
if ((cp_coher_cntl ||
(flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
- RADV_CMD_FLAG_INV_VMEM_L1 |
- RADV_CMD_FLAG_INV_GLOBAL_L2 |
- RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) &&
+ RADV_CMD_FLAG_INV_VCACHE |
+ RADV_CMD_FLAG_INV_L2 |
+ RADV_CMD_FLAG_WB_L2))) &&
!is_mec) {
radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
radeon_emit(cs, 0);
}
- if ((flush_bits & RADV_CMD_FLAG_INV_GLOBAL_L2) ||
- (chip_class <= CIK && (flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2))) {
+ if ((flush_bits & RADV_CMD_FLAG_INV_L2) ||
+ (chip_class <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
si_emit_acquire_mem(cs, is_mec, chip_class >= GFX9,
cp_coher_cntl |
S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_TCL1_ACTION_ENA(1) |
- S_0301F0_TC_WB_ACTION_ENA(chip_class >= VI));
+ S_0301F0_TC_WB_ACTION_ENA(chip_class >= GFX8));
cp_coher_cntl = 0;
} else {
- if(flush_bits & RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2) {
+ if(flush_bits & RADV_CMD_FLAG_WB_L2) {
/* WB = write-back
* NC = apply to non-coherent MTYPEs
* (i.e. MTYPE <= 1, which is what we use everywhere)
S_0301F0_TC_NC_ACTION_ENA(1));
cp_coher_cntl = 0;
}
- if (flush_bits & RADV_CMD_FLAG_INV_VMEM_L1) {
+ if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
si_emit_acquire_mem(cs, is_mec,
chip_class >= GFX9,
cp_coher_cntl |
if (!cmd_buffer->state.flush_bits)
return;
- enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
- uint32_t *ptr = NULL;
- uint64_t va = 0;
- if (chip_class == GFX9) {
- va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + cmd_buffer->gfx9_fence_offset;
- ptr = &cmd_buffer->gfx9_fence_idx;
- }
si_cs_emit_cache_flush(cmd_buffer->cs,
cmd_buffer->device->physical_device->rad_info.chip_class,
- ptr, va,
+ &cmd_buffer->gfx9_fence_idx,
+ cmd_buffer->gfx9_fence_va,
radv_cmd_buffer_uses_mec(cmd_buffer),
cmd_buffer->state.flush_bits,
cmd_buffer->gfx9_eop_bug_va);
if (unlikely(cmd_buffer->device->trace_bo))
radv_cmd_buffer_trace_emit(cmd_buffer);
+ /* Clear the caches that have been flushed to avoid syncing too much
+ * when there is some pending active queries.
+ */
+ cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
+
cmd_buffer->state.flush_bits = 0;
+
+ /* If the driver used a compute shader for resetting a query pool, it
+ * should be finished at this point.
+ */
+ cmd_buffer->pending_reset_query = false;
}
/* sets the CP predication state using a boolean stored at va */
void
si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer,
- bool inverted, uint64_t va)
+ bool draw_visible, uint64_t va)
{
uint32_t op = 0;
if (va) {
op = PRED_OP(PREDICATION_OP_BOOL64);
- /* By default, our internal rendering commands are discarded
- * only if the predicate is non-zero (ie. DRAW_VISIBLE). But
- * VK_EXT_conditional_rendering also allows to discard commands
- * when the predicate is zero, which means we have to use a
- * different flag.
+ /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
+ * zero, all rendering commands are discarded. Otherwise, they
+ * are discarded if the value is non zero.
*/
- op |= inverted ? PREDICATION_DRAW_VISIBLE :
- PREDICATION_DRAW_NOT_VISIBLE;
+ op |= draw_visible ? PREDICATION_DRAW_VISIBLE :
+ PREDICATION_DRAW_NOT_VISIBLE;
}
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
else if (flags & CP_DMA_USE_L2)
header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, cmd_buffer->state.predicating));
radeon_emit(cs, header);
radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
size + skipped_size + realign_size,
&dma_flags);
+ dma_flags &= ~CP_DMA_SYNC;
+
si_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va,
byte_count, dma_flags);
void si_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
{
- if (cmd_buffer->device->physical_device->rad_info.chip_class < CIK)
+ if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX7)
return;
if (!cmd_buffer->state.dma_is_busy)
/* For MSAA sample positions. */
#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
- (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
- (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
- (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
+ ((((unsigned)(s0x) & 0xf) << 0) | (((unsigned)(s0y) & 0xf) << 4) | \
+ (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
+ (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
(((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
-
-/* 2xMSAA
- * There are two locations (4, 4), (-4, -4). */
-const uint32_t eg_sample_locs_2x[4] = {
- FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
- FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
- FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
- FILL_SREG(4, 4, -4, -4, 4, 4, -4, -4),
-};
-const unsigned eg_max_dist_2x = 4;
-/* 4xMSAA
- * There are 4 locations: (-2, 6), (6, -2), (-6, 2), (2, 6). */
-const uint32_t eg_sample_locs_4x[4] = {
- FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
- FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
- FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
- FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6),
+/* For obtaining location coordinates from registers */
+#define SEXT4(x) ((int)((x) | ((x) & 0x8 ? 0xfffffff0 : 0)))
+#define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index) * 4)) & 0xf)
+#define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
+#define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
+
+/* 1x MSAA */
+static const uint32_t sample_locs_1x =
+ FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
+static const unsigned max_dist_1x = 0;
+static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
+
+/* 2xMSAA */
+static const uint32_t sample_locs_2x =
+ FILL_SREG(4,4, -4, -4, 0, 0, 0, 0);
+static const unsigned max_dist_2x = 4;
+static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
+
+/* 4xMSAA */
+static const uint32_t sample_locs_4x =
+ FILL_SREG(-2,-6, 6, -2, -6, 2, 2, 6);
+static const unsigned max_dist_4x = 6;
+static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
+
+/* 8xMSAA */
+static const uint32_t sample_locs_8x[] = {
+ FILL_SREG( 1,-3, -1, 3, 5, 1, -3,-5),
+ FILL_SREG(-5, 5, -7,-1, 3, 7, 7,-7),
+ /* The following are unused by hardware, but we emit them to IBs
+ * instead of multiple SET_CONTEXT_REG packets. */
+ 0,
+ 0,
};
-const unsigned eg_max_dist_4x = 6;
-
-/* Cayman 8xMSAA */
-static const uint32_t cm_sample_locs_8x[] = {
- FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
- FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
- FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
- FILL_SREG( 1, -3, -1, 3, 5, 1, -3, -5),
- FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
- FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
- FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
- FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
-};
-static const unsigned cm_max_dist_8x = 8;
-/* Cayman 16xMSAA */
-static const uint32_t cm_sample_locs_16x[] = {
- FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
- FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
- FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
- FILL_SREG( 1, 1, -1, -3, -3, 2, 4, -1),
- FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
- FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
- FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
- FILL_SREG(-5, -2, 2, 5, 5, 3, 3, -5),
- FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
- FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
- FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
- FILL_SREG(-2, 6, 0, -7, -4, -6, -6, 4),
- FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
- FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
- FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
- FILL_SREG(-8, 0, 7, -4, 6, 7, -7, -8),
-};
-static const unsigned cm_max_dist_16x = 8;
+static const unsigned max_dist_8x = 7;
+static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
-unsigned radv_cayman_get_maxdist(int log_samples)
+unsigned radv_get_default_max_sample_dist(int log_samples)
{
unsigned max_dist[] = {
- 0,
- eg_max_dist_2x,
- eg_max_dist_4x,
- cm_max_dist_8x,
- cm_max_dist_16x
+ max_dist_1x,
+ max_dist_2x,
+ max_dist_4x,
+ max_dist_8x,
};
return max_dist[log_samples];
}
-void radv_cayman_emit_msaa_sample_locs(struct radeon_cmdbuf *cs, int nr_samples)
+void radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
{
switch (nr_samples) {
default:
case 1:
- radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
- radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
- radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
- radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
+ radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+ radeon_emit(cs, (uint32_t)centroid_priority_1x);
+ radeon_emit(cs, centroid_priority_1x >> 32);
+ radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
+ radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
+ radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
+ radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
break;
case 2:
- radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
- radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
- radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
- radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
+ radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+ radeon_emit(cs, (uint32_t)centroid_priority_2x);
+ radeon_emit(cs, centroid_priority_2x >> 32);
+ radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
+ radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
+ radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
+ radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
break;
case 4:
- radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
- radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
- radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
- radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
+ radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+ radeon_emit(cs, (uint32_t)centroid_priority_4x);
+ radeon_emit(cs, centroid_priority_4x >> 32);
+ radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
+ radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
+ radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
+ radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
break;
case 8:
+ radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
+ radeon_emit(cs, (uint32_t)centroid_priority_8x);
+ radeon_emit(cs, centroid_priority_8x >> 32);
radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
- radeon_emit(cs, cm_sample_locs_8x[0]);
- radeon_emit(cs, cm_sample_locs_8x[4]);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, cm_sample_locs_8x[1]);
- radeon_emit(cs, cm_sample_locs_8x[5]);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, cm_sample_locs_8x[2]);
- radeon_emit(cs, cm_sample_locs_8x[6]);
- radeon_emit(cs, 0);
- radeon_emit(cs, 0);
- radeon_emit(cs, cm_sample_locs_8x[3]);
- radeon_emit(cs, cm_sample_locs_8x[7]);
- break;
- case 16:
- radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
- radeon_emit(cs, cm_sample_locs_16x[0]);
- radeon_emit(cs, cm_sample_locs_16x[4]);
- radeon_emit(cs, cm_sample_locs_16x[8]);
- radeon_emit(cs, cm_sample_locs_16x[12]);
- radeon_emit(cs, cm_sample_locs_16x[1]);
- radeon_emit(cs, cm_sample_locs_16x[5]);
- radeon_emit(cs, cm_sample_locs_16x[9]);
- radeon_emit(cs, cm_sample_locs_16x[13]);
- radeon_emit(cs, cm_sample_locs_16x[2]);
- radeon_emit(cs, cm_sample_locs_16x[6]);
- radeon_emit(cs, cm_sample_locs_16x[10]);
- radeon_emit(cs, cm_sample_locs_16x[14]);
- radeon_emit(cs, cm_sample_locs_16x[3]);
- radeon_emit(cs, cm_sample_locs_16x[7]);
- radeon_emit(cs, cm_sample_locs_16x[11]);
- radeon_emit(cs, cm_sample_locs_16x[15]);
+ radeon_emit_array(cs, sample_locs_8x, 4);
+ radeon_emit_array(cs, sample_locs_8x, 4);
+ radeon_emit_array(cs, sample_locs_8x, 4);
+ radeon_emit_array(cs, sample_locs_8x, 2);
break;
}
}
-static void radv_cayman_get_sample_position(struct radv_device *device,
- unsigned sample_count,
- unsigned sample_index, float *out_value)
+static void radv_get_sample_position(struct radv_device *device,
+ unsigned sample_count,
+ unsigned sample_index, float *out_value)
{
- int offset, index;
- struct {
- int idx:4;
- } val;
+ const uint32_t *sample_locs;
+
switch (sample_count) {
case 1:
default:
- out_value[0] = out_value[1] = 0.5;
+ sample_locs = &sample_locs_1x;
break;
case 2:
- offset = 4 * (sample_index * 2);
- val.idx = (eg_sample_locs_2x[0] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (eg_sample_locs_2x[0] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
+ sample_locs = &sample_locs_2x;
break;
case 4:
- offset = 4 * (sample_index * 2);
- val.idx = (eg_sample_locs_4x[0] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (eg_sample_locs_4x[0] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
+ sample_locs = &sample_locs_4x;
break;
case 8:
- offset = 4 * (sample_index % 4 * 2);
- index = (sample_index / 4) * 4;
- val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
- break;
- case 16:
- offset = 4 * (sample_index % 4 * 2);
- index = (sample_index / 4) * 4;
- val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
- out_value[0] = (float)(val.idx + 8) / 16.0f;
- val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
- out_value[1] = (float)(val.idx + 8) / 16.0f;
+ sample_locs = sample_locs_8x;
break;
}
+
+ out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
+ out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
}
void radv_device_init_msaa(struct radv_device *device)
{
int i;
- radv_cayman_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
+
+ radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
for (i = 0; i < 2; i++)
- radv_cayman_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
+ radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
for (i = 0; i < 4; i++)
- radv_cayman_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
+ radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
for (i = 0; i < 8; i++)
- radv_cayman_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
- for (i = 0; i < 16; i++)
- radv_cayman_get_sample_position(device, 16, i, device->sample_locations_16x[i]);
+ radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
}