radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initialization
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 25 Jun 2019 13:38:44 +0000 (15:38 +0200)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sun, 7 Jul 2019 15:51:32 +0000 (17:51 +0200)
The value doesn't need to be updated for tess.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_pipeline.c
src/amd/vulkan/si_cmd_buffer.c

index 2d54ebe05260ccf6d74f6c53b3ccdc218ccf22f6..701edd07572c967e7de92e0e67cc522e751cfabf 100644 (file)
@@ -3434,7 +3434,8 @@ static void
 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
                                        struct radv_pipeline *pipeline)
 {
-       if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10)
+       if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
+           pipeline->device->physical_device->rad_info.chip_class >= GFX10)
                return;
 
        unsigned vtx_reuse_depth = 30;
index 91015f9f01e89289d139dea2076200946337ae82..91a1db4fc840cfd10b391012247fc9b6dd5b37c8 100644 (file)
@@ -321,6 +321,7 @@ si_emit_graphics(struct radv_physical_device *physical_device,
        }
 
        if (physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
                radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
                                       physical_device->rad_info.pa_sc_tile_steering_override);
                radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,