radv/gfx10: emit VGT_VERTEX_REUSE_BLOCK_CNTL during gfx initialization

[mesa.git] / src / amd / vulkan / si_cmd_buffer.c

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index a3ed09a157c6db884fa15229b3cb007108a07045..91a1db4fc840cfd10b391012247fc9b6dd5b37c8 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -88,7 +88,8 @@ si_emit_compute(struct radv_physical_device *physical_device,
        radeon_emit(cs, 0);
 
        radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
-       /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */
+       /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
+        * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
        radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
        radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff));
 
@@ -102,6 +103,9 @@ si_emit_compute(struct radv_physical_device *physical_device,
                            S_00B858_SH1_CU_EN(0xffff));
        }
 
+       if (physical_device->rad_info.chip_class >= GFX10)
+               radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
+
        /* This register has been moved to R_00CD20_COMPUTE_MAX_WAVE_ID
         * and is now per pipe, so it should be handled in the
         * kernel if we want to use something other than the default value,
@@ -237,7 +241,11 @@ si_emit_graphics(struct radv_physical_device *physical_device,
                               S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
                               S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
 
-       if (physical_device->rad_info.chip_class >= GFX9) {
+       if (physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
+               radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
+               radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
+       } else if (physical_device->rad_info.chip_class >= GFX9) {
                radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
                radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
                radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
@@ -253,6 +261,19 @@ si_emit_graphics(struct radv_physical_device *physical_device,
        }
 
        if (physical_device->rad_info.chip_class >= GFX7) {
+               if (physical_device->rad_info.chip_class >= GFX10) {
+                       /* Logical CUs 16 - 31 */
+                       radeon_set_sh_reg(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
+                                         S_00B404_CU_EN(0xffff));
+                       radeon_set_sh_reg(cs, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
+                                         S_00B204_CU_EN(0xffff) |
+                                         S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
+                       radeon_set_sh_reg(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
+                                         S_00B104_CU_EN(0xffff));
+                       radeon_set_sh_reg(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
+                                         S_00B004_CU_EN(0xffff));
+               }
+
                if (physical_device->rad_info.chip_class >= GFX9) {
                        radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
                                          S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
@@ -300,6 +321,7 @@ si_emit_graphics(struct radv_physical_device *physical_device,
        }
 
        if (physical_device->rad_info.chip_class >= GFX10) {
+               radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
                radeon_set_context_reg(cs, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
                                       physical_device->rad_info.pa_sc_tile_steering_override);
                radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,