arch: [Patch 1/5] Added RISC-V base instruction set RV64I

[gem5.git] / src / base / loader / elf_object.cc

diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index 43c00b19e2756af7ff57da5e22ac7fad39388aca..df9134e9efb05f6d247de1b42d955bcfb625a39d 100644 (file)
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -111,6 +111,8 @@ ElfObject::tryFile(const std::string &fname, size_t len, uint8_t *data,
     } else if (ehdr.e_machine == EM_AARCH64 &&
                ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
         arch = Arm64;
+    } else if (ehdr.e_machine == EM_RISCV) {
+        arch = Riscv;
     } else if (ehdr.e_machine == EM_PPC &&
                ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
         arch = Power;