}
}
-static void
-vtn_handle_bitcast(struct vtn_builder *b, struct vtn_ssa_value *dest,
- struct nir_ssa_def *src)
-{
- if (glsl_get_vector_elements(dest->type) == src->num_components) {
- /* From the definition of OpBitcast in the SPIR-V 1.2 spec:
- *
- * "If Result Type has the same number of components as Operand, they
- * must also have the same component width, and results are computed per
- * component."
- */
- dest->def = nir_imov(&b->nb, src);
- return;
- }
-
- /* From the definition of OpBitcast in the SPIR-V 1.2 spec:
- *
- * "If Result Type has a different number of components than Operand, the
- * total number of bits in Result Type must equal the total number of bits
- * in Operand. Let L be the type, either Result Type or Operand’s type, that
- * has the larger number of components. Let S be the other type, with the
- * smaller number of components. The number of components in L must be an
- * integer multiple of the number of components in S. The first component
- * (that is, the only or lowest-numbered component) of S maps to the first
- * components of L, and so on, up to the last component of S mapping to the
- * last components of L. Within this mapping, any single component of S
- * (mapping to multiple components of L) maps its lower-ordered bits to the
- * lower-numbered components of L."
- */
- unsigned src_bit_size = src->bit_size;
- unsigned dest_bit_size = glsl_get_bit_size(dest->type);
- unsigned src_components = src->num_components;
- unsigned dest_components = glsl_get_vector_elements(dest->type);
- vtn_assert(src_bit_size * src_components == dest_bit_size * dest_components);
-
- nir_ssa_def *dest_chan[4];
- if (src_bit_size > dest_bit_size) {
- vtn_assert(src_bit_size % dest_bit_size == 0);
- unsigned divisor = src_bit_size / dest_bit_size;
- for (unsigned comp = 0; comp < src_components; comp++) {
- vtn_assert(src_bit_size == 64);
- vtn_assert(dest_bit_size == 32);
- nir_ssa_def *split =
- nir_unpack_64_2x32(&b->nb, nir_channel(&b->nb, src, comp));
- for (unsigned i = 0; i < divisor; i++)
- dest_chan[divisor * comp + i] = nir_channel(&b->nb, split, i);
- }
- } else {
- vtn_assert(dest_bit_size % src_bit_size == 0);
- unsigned divisor = dest_bit_size / src_bit_size;
- for (unsigned comp = 0; comp < dest_components; comp++) {
- unsigned channels = ((1 << divisor) - 1) << (comp * divisor);
- nir_ssa_def *src_chan =
- nir_channels(&b->nb, src, channels);
- vtn_assert(dest_bit_size == 64);
- vtn_assert(src_bit_size == 32);
- dest_chan[comp] = nir_pack_64_2x32(&b->nb, src_chan);
- }
- }
- dest->def = nir_vec(&b->nb, dest_chan, dest_components);
-}
-
nir_op
vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b,
SpvOp opcode, bool *swap,
case SpvOpDPdyCoarse: return nir_op_fddy_coarse;
default:
- vtn_fail("No NIR equivalent");
+ vtn_fail("No NIR equivalent: %u", opcode);
}
}
if (glsl_type_is_matrix(vtn_src[0]->type) ||
(num_inputs >= 2 && glsl_type_is_matrix(vtn_src[1]->type))) {
vtn_handle_matrix_alu(b, opcode, val, vtn_src[0], vtn_src[1]);
- b->nb.exact = false;
+ b->nb.exact = b->exact;
return;
}
default: vtn_fail("invalid number of components");
}
val->ssa->def = nir_build_alu(&b->nb, op, src[0],
- nir_imm_int(&b->nb, NIR_FALSE),
+ nir_imm_false(&b->nb),
NULL, NULL);
}
break;
default: vtn_fail("invalid number of components");
}
val->ssa->def = nir_build_alu(&b->nb, op, src[0],
- nir_imm_int(&b->nb, NIR_TRUE),
+ nir_imm_true(&b->nb),
NULL, NULL);
}
break;
val->ssa->elems[1]->def = nir_usub_borrow(&b->nb, src[0], src[1]);
break;
- case SpvOpUMulExtended:
+ case SpvOpUMulExtended: {
vtn_assert(glsl_type_is_struct(val->ssa->type));
- val->ssa->elems[0]->def = nir_imul(&b->nb, src[0], src[1]);
- val->ssa->elems[1]->def = nir_umul_high(&b->nb, src[0], src[1]);
+ nir_ssa_def *umul = nir_umul_2x32_64(&b->nb, src[0], src[1]);
+ val->ssa->elems[0]->def = nir_unpack_64_2x32_split_x(&b->nb, umul);
+ val->ssa->elems[1]->def = nir_unpack_64_2x32_split_y(&b->nb, umul);
break;
+ }
- case SpvOpSMulExtended:
+ case SpvOpSMulExtended: {
vtn_assert(glsl_type_is_struct(val->ssa->type));
- val->ssa->elems[0]->def = nir_imul(&b->nb, src[0], src[1]);
- val->ssa->elems[1]->def = nir_imul_high(&b->nb, src[0], src[1]);
+ nir_ssa_def *smul = nir_imul_2x32_64(&b->nb, src[0], src[1]);
+ val->ssa->elems[0]->def = nir_unpack_64_2x32_split_x(&b->nb, smul);
+ val->ssa->elems[1]->def = nir_unpack_64_2x32_split_y(&b->nb, smul);
break;
+ }
case SpvOpFwidth:
val->ssa->def = nir_fadd(&b->nb,
}
case SpvOpBitcast:
- vtn_handle_bitcast(b, val->ssa, src[0]);
+ /* From the definition of OpBitcast in the SPIR-V 1.2 spec:
+ *
+ * "If Result Type has the same number of components as Operand, they
+ * must also have the same component width, and results are computed
+ * per component.
+ *
+ * If Result Type has a different number of components than Operand,
+ * the total number of bits in Result Type must equal the total
+ * number of bits in Operand. Let L be the type, either Result Type
+ * or Operand’s type, that has the larger number of components. Let S
+ * be the other type, with the smaller number of components. The
+ * number of components in L must be an integer multiple of the
+ * number of components in S. The first component (that is, the only
+ * or lowest-numbered component) of S maps to the first components of
+ * L, and so on, up to the last component of S mapping to the last
+ * components of L. Within this mapping, any single component of S
+ * (mapping to multiple components of L) maps its lower-ordered bits
+ * to the lower-numbered components of L."
+ */
+ vtn_fail_if(src[0]->num_components * src[0]->bit_size !=
+ glsl_get_vector_elements(type) * glsl_get_bit_size(type),
+ "Source and destination of OpBitcast must have the same "
+ "total number of bits");
+ val->ssa->def = nir_bitcast_vector(&b->nb, src[0],
+ glsl_get_bit_size(type));
break;
case SpvOpFConvert: {
break;
}
+ case SpvOpBitFieldInsert:
+ case SpvOpBitFieldSExtract:
+ case SpvOpBitFieldUExtract:
+ case SpvOpShiftLeftLogical:
+ case SpvOpShiftRightArithmetic:
+ case SpvOpShiftRightLogical: {
+ bool swap;
+ unsigned src0_bit_size = glsl_get_bit_size(vtn_src[0]->type);
+ unsigned dst_bit_size = glsl_get_bit_size(type);
+ nir_op op = vtn_nir_alu_op_for_spirv_opcode(b, opcode, &swap,
+ src0_bit_size, dst_bit_size);
+
+ assert (op == nir_op_ushr || op == nir_op_ishr || op == nir_op_ishl ||
+ op == nir_op_bitfield_insert || op == nir_op_ubitfield_extract ||
+ op == nir_op_ibitfield_extract);
+
+ for (unsigned i = 0; i < nir_op_infos[op].num_inputs; i++) {
+ unsigned src_bit_size =
+ nir_alu_type_get_type_size(nir_op_infos[op].input_types[i]);
+ if (src_bit_size == 0)
+ continue;
+ if (src_bit_size != src[i]->bit_size) {
+ assert(src_bit_size == 32);
+ /* Convert the Shift, Offset and Count operands to 32 bits, which is the bitsize
+ * supported by the NIR instructions. See discussion here:
+ *
+ * https://lists.freedesktop.org/archives/mesa-dev/2018-April/193026.html
+ */
+ src[i] = nir_u2u32(&b->nb, src[i]);
+ }
+ }
+ val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]);
+ break;
+ }
+
+ case SpvOpSignBitSet: {
+ unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
+ if (src[0]->num_components == 1)
+ val->ssa->def =
+ nir_ushr(&b->nb, src[0], nir_imm_int(&b->nb, src_bit_size - 1));
+ else
+ val->ssa->def =
+ nir_ishr(&b->nb, src[0], nir_imm_int(&b->nb, src_bit_size - 1));
+
+ if (src_bit_size != 32)
+ val->ssa->def = nir_u2u32(&b->nb, val->ssa->def);
+
+ break;
+ }
+
default: {
bool swap;
unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type);
src[1] = tmp;
}
+ switch (op) {
+ case nir_op_ishl:
+ case nir_op_ishr:
+ case nir_op_ushr:
+ if (src[1]->bit_size != 32)
+ src[1] = nir_u2u32(&b->nb, src[1]);
+ break;
+ default:
+ break;
+ }
+
val->ssa->def = nir_build_alu(&b->nb, op, src[0], src[1], src[2], src[3]);
break;
} /* default */
}
- b->nb.exact = false;
+ b->nb.exact = b->exact;
}
projects / mesa.git / blobdiff