ir3: Plumb through bindless support

[mesa.git] / src / freedreno / ir3 / ir3_cp.c

diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c
index b7fb86ec791ab3c944bf023140088050edce2e74..782be12c1928ee1a32797338c00b0a9dcfa5dfa9 100644 (file)
--- a/src/freedreno/ir3/ir3_cp.c
+++ b/src/freedreno/ir3/ir3_cp.c
@@ -229,6 +229,9 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n,
                        if (instr->opc == OPC_STLW && n == 0)
                                return false;
 
+                       if (instr->opc == OPC_LDLW && n == 0)
+                               return false;
+
                        /* disallow CP into anything but the SSBO slot argument for
                         * atomics:
                         */
@@ -241,10 +244,10 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n,
                        if (instr->opc == OPC_STG && (instr->flags & IR3_INSTR_G) && (n != 2))
                                return false;
 
-                       /* as with atomics, ldib on a6xx can only have immediate for
-                        * SSBO slot argument
+                       /* as with atomics, ldib and ldc on a6xx can only have immediate
+                        * for SSBO slot argument
                         */
-                       if ((instr->opc == OPC_LDIB) && (n != 0))
+                       if ((instr->opc == OPC_LDIB || instr->opc == OPC_LDC) && (n != 0))
                                return false;
                }
 
@@ -305,6 +308,12 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
 
        reg = ir3_reg_clone(ctx->shader, reg);
 
+       /* Half constant registers seems to handle only 32-bit values
+        * within floating-point opcodes. So convert back to 32-bit values.
+        */
+       if (f_opcode && (new_flags & IR3_REG_HALF))
+               reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
+
        /* in some cases, there are restrictions on (abs)/(neg) plus const..
         * so just evaluate those and clear the flags:
         */
@@ -350,12 +359,6 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
                swiz = i % 4;
                idx  = i / 4;
 
-               /* Half constant registers seems to handle only 32-bit values
-                * within floating-point opcodes. So convert back to 32-bit values. */
-               if (f_opcode && (new_flags & IR3_REG_HALF)) {
-                       reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
-               }
-
                const_state->immediates[idx].val[swiz] = reg->uim_val;
                const_state->immediates_count = idx + 1;
                const_state->immediate_idx++;
@@ -523,6 +526,17 @@ reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
                                        (src_reg->array.offset == 0))
                                return false;
 
+                       /* When narrowing constant from 32b to 16b, it seems
+                        * to work only for float. So we should do this only with
+                        * float opcodes.
+                        */
+                       if (src->cat1.dst_type == TYPE_F16) {
+                               if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
+                                       return false;
+                               if (!ir3_cat2_float(instr->opc) && !ir3_cat3_float(instr->opc))
+                                       return false;
+                       }
+
                        src_reg = ir3_reg_clone(instr->block->shader, src_reg);
                        src_reg->flags = new_flags;
                        instr->regs[n+1] = src_reg;
@@ -632,7 +646,7 @@ instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
        bool progress;
        do {
                progress = false;
-               foreach_src_n(reg, n, instr) {
+               foreach_src_n (reg, n, instr) {
                        struct ir3_instruction *src = ssa(reg);
 
                        if (!src)
@@ -699,12 +713,14 @@ instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
                }
        }
 
-       /* Handle converting a sam.s2en (taking samp/tex idx params via
-        * register) into a normal sam (encoding immediate samp/tex idx)
-        * if they are immediate.  This saves some instructions and regs
-        * in the common case where we know samp/tex at compile time:
+       /* Handle converting a sam.s2en (taking samp/tex idx params via register)
+        * into a normal sam (encoding immediate samp/tex idx) if they are
+        * immediate. This saves some instructions and regs in the common case
+        * where we know samp/tex at compile time. This needs to be done in the
+        * frontend for bindless tex, though, so don't replicate it here.
         */
        if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
+                       !(instr->flags & IR3_INSTR_B) &&
                        !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
                /* The first src will be a collect, if both of it's
                 * two sources are mov from imm, then we can
@@ -756,7 +772,7 @@ ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
                         */
                        debug_assert(instr->deps_count == 0);
 
-                       foreach_ssa_src(src, instr) {
+                       foreach_ssa_src (src, instr) {
                                src->use_count++;
                        }
                }
@@ -765,7 +781,7 @@ ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so)
        ir3_clear_mark(ir);
 
        struct ir3_instruction *out;
-       foreach_output_n(out, n, ir) {
+       foreach_output_n (out, n, ir) {
                instr_cp(&ctx, out);
                ir->outputs[n] = eliminate_output_mov(out);
        }