freedreno/ir3: small cleanup
[mesa.git] / src / freedreno / ir3 / ir3_nir.c
index 804196f63e9255baba7708f2bb800a49ff843291..437f196bbe0504221748f41baa0dd2808bc3ef80 100644 (file)
 
 
 #include "util/debug.h"
+#include "util/u_math.h"
 
 #include "ir3_nir.h"
 #include "ir3_compiler.h"
 #include "ir3_shader.h"
 
+static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
+
 static const nir_shader_compiler_options options = {
                .lower_fpow = true,
                .lower_scmp = true,
                .lower_flrp32 = true,
                .lower_flrp64 = true,
                .lower_ffract = true,
-               .lower_fmod32 = true,
-               .lower_fmod64 = true,
+               .lower_fmod = true,
                .lower_fdiv = true,
                .lower_isign = true,
                .lower_ldexp = true,
@@ -52,7 +54,6 @@ static const nir_shader_compiler_options options = {
                .lower_helper_invocation = true,
                .lower_bitfield_insert_to_shifts = true,
                .lower_bitfield_extract_to_shifts = true,
-               .lower_bfm = true,
                .use_interpolated_input_intrinsics = true,
 };
 
@@ -63,8 +64,7 @@ static const nir_shader_compiler_options options_a6xx = {
                .lower_flrp32 = true,
                .lower_flrp64 = true,
                .lower_ffract = true,
-               .lower_fmod32 = true,
-               .lower_fmod64 = true,
+               .lower_fmod = true,
                .lower_fdiv = true,
                .lower_isign = true,
                .lower_ldexp = true,
@@ -78,7 +78,6 @@ static const nir_shader_compiler_options options_a6xx = {
                .lower_helper_invocation = true,
                .lower_bitfield_insert_to_shifts = true,
                .lower_bitfield_extract_to_shifts = true,
-               .lower_bfm = true,
                .use_interpolated_input_intrinsics = true,
 };
 
@@ -123,7 +122,7 @@ ir3_optimize_loop(nir_shader *s)
                OPT_V(s, nir_lower_vars_to_ssa);
                progress |= OPT(s, nir_opt_copy_prop_vars);
                progress |= OPT(s, nir_opt_dead_write_vars);
-               progress |= OPT(s, nir_lower_alu_to_scalar);
+               progress |= OPT(s, nir_lower_alu_to_scalar, NULL);
                progress |= OPT(s, nir_lower_phis_to_scalar);
 
                progress |= OPT(s, nir_copy_prop);
@@ -173,7 +172,7 @@ ir3_optimize_loop(nir_shader *s)
        } while (progress);
 }
 
-struct nir_shader *
+void
 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
                const struct ir3_shader_key *key)
 {
@@ -273,10 +272,16 @@ ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 
        nir_sweep(s);
 
-       return s;
+       /* The first time thru, when not creating variant, do the one-time
+        * const_state layout setup.  This should be done after ubo range
+        * analysis.
+        */
+       if (!key) {
+               ir3_setup_const_state(shader, s);
+       }
 }
 
-void
+static void
 ir3_nir_scan_driver_consts(nir_shader *shader,
                struct ir3_const_state *layout)
 {
@@ -321,6 +326,13 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
                                                layout->image_dims.count;
                                        layout->image_dims.count += 3; /* three const per */
                                        break;
+                               case nir_intrinsic_load_ubo:
+                                       if (nir_src_is_const(intr->src[0])) {
+                                               layout->num_ubos = MAX2(layout->num_ubos,
+                                                               nir_src_as_uint(intr->src[0]) + 1);
+                                       } else {
+                                               layout->num_ubos = shader->info.num_ubos;
+                                       }
                                default:
                                        break;
                                }
@@ -328,3 +340,54 @@ ir3_nir_scan_driver_consts(nir_shader *shader,
                }
        }
 }
+
+static void
+ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
+{
+       struct ir3_compiler *compiler = shader->compiler;
+       struct ir3_const_state *const_state = &shader->const_state;
+
+       memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
+
+       ir3_nir_scan_driver_consts(nir, const_state);
+
+       debug_assert((shader->ubo_state.size % 16) == 0);
+       unsigned constoff = align(shader->ubo_state.size / 16, 4);
+       unsigned ptrsz = ir3_pointer_size(compiler);
+
+       if (const_state->num_ubos > 0) {
+               const_state->offsets.ubo = constoff;
+               constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
+       }
+
+       if (const_state->ssbo_size.count > 0) {
+               unsigned cnt = const_state->ssbo_size.count;
+               const_state->offsets.ssbo_sizes = constoff;
+               constoff += align(cnt, 4) / 4;
+       }
+
+       if (const_state->image_dims.count > 0) {
+               unsigned cnt = const_state->image_dims.count;
+               const_state->offsets.image_dims = constoff;
+               constoff += align(cnt, 4) / 4;
+       }
+
+       unsigned num_driver_params = 0;
+       if (shader->type == MESA_SHADER_VERTEX) {
+               num_driver_params = IR3_DP_VS_COUNT;
+       } else if (shader->type == MESA_SHADER_COMPUTE) {
+               num_driver_params = IR3_DP_CS_COUNT;
+       }
+
+       const_state->offsets.driver_param = constoff;
+       constoff += align(num_driver_params, 4) / 4;
+
+       if ((shader->type == MESA_SHADER_VERTEX) &&
+                       (compiler->gpu_id < 500) &&
+                       shader->stream_output.num_outputs > 0) {
+               const_state->offsets.tfbo = constoff;
+               constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
+       }
+
+       const_state->offsets.immediate = constoff;
+}