* Rob Clark <robclark@freedesktop.org>
*/
+#include "util/u_atomic.h"
#include "util/u_string.h"
#include "util/u_memory.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "drm/freedreno_drmif.h"
ir3_destroy(v->ir);
if (v->bo)
fd_bo_del(v->bo);
- if (v->immediates)
- free(v->immediates);
free(v);
}
}
for (i = 0; i < v->outputs_count; i++) {
+ /* for ex, VS shaders with tess don't have normal varying outs: */
+ if (!VALIDREG(v->outputs[i].regid))
+ continue;
int32_t regid = v->outputs[i].regid + 3;
if (v->outputs[i].half) {
if (gpu_id < 500) {
v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
}
}
+
+ for (i = 0; i < v->num_sampler_prefetch; i++) {
+ unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
+ int32_t regid = v->sampler_prefetch[i].dst + n;
+ if (v->sampler_prefetch[i].half_precision) {
+ if (gpu_id < 500) {
+ v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
+ } else {
+ v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
+ }
+ } else {
+ v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
+ }
+ }
}
/* wrapper for ir3_assemble() which does some info fixup based on
v->bo = fd_bo_new(compiler->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
DRM_FREEDRENO_GEM_TYPE_KMEM,
- "%s:%s", ir3_shader_stage(v->shader), info->name);
+ "%s:%s", ir3_shader_stage(v), info->name);
memcpy(fd_bo_map(v->bo), bin, sz);
- if (ir3_shader_debug & IR3_DBG_DISASM) {
- struct ir3_shader_key key = v->key;
- printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
- v->binning_pass, key.color_two_side, key.half_precision);
- ir3_shader_disasm(v, bin, stdout);
- }
-
if (shader_debug_enabled(v->shader->type)) {
- fprintf(stderr, "Native code for unnamed %s shader %s:\n",
- _mesa_shader_stage_to_string(v->shader->type),
- v->shader->nir->info.name);
+ fprintf(stdout, "Native code for unnamed %s shader %s:\n",
+ ir3_shader_stage(v), v->shader->nir->info.name);
if (v->shader->type == MESA_SHADER_FRAGMENT)
- fprintf(stderr, "SIMD0\n");
- ir3_shader_disasm(v, bin, stderr);
+ fprintf(stdout, "SIMD0\n");
+ ir3_shader_disasm(v, bin, stdout);
}
free(bin);
v->ir = NULL;
}
+/*
+ * For creating normal shader variants, 'nonbinning' is NULL. For
+ * creating binning pass shader, it is link to corresponding normal
+ * (non-binning) variant.
+ */
static struct ir3_shader_variant *
create_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
- bool binning_pass)
+ struct ir3_shader_variant *nonbinning)
{
struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
int ret;
v->id = ++shader->variant_count;
v->shader = shader;
- v->binning_pass = binning_pass;
+ v->binning_pass = !!nonbinning;
+ v->nonbinning = nonbinning;
v->key = *key;
v->type = shader->type;
return v;
/* compile new variant if it doesn't exist already: */
- v = create_variant(shader, key, false);
+ v = create_variant(shader, key, NULL);
if (v) {
v->next = shader->variants;
shader->variants = v;
ir3_shader_get_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
bool binning_pass, bool *created)
{
+ mtx_lock(&shader->variants_lock);
struct ir3_shader_variant *v =
shader_variant(shader, key, created);
if (v && binning_pass) {
- if (!v->binning)
- v->binning = create_variant(shader, key, true);
+ if (!v->binning) {
+ v->binning = create_variant(shader, key, v);
+ *created = true;
+ }
+ mtx_unlock(&shader->variants_lock);
return v->binning;
}
+ mtx_unlock(&shader->variants_lock);
return v;
}
v = v->next;
delete_variant(t);
}
+ free(shader->const_state.immediates);
ralloc_free(shader->nir);
+ mtx_destroy(&shader->variants_lock);
free(shader);
}
+static bool
+lower_output_var(nir_shader *nir, int location)
+{
+ nir_foreach_variable (var, &nir->outputs) {
+ if (var->data.driver_location == location &&
+ ((var->data.precision == GLSL_PRECISION_MEDIUM) ||
+ (var->data.precision == GLSL_PRECISION_LOW))) {
+ if (glsl_get_base_type(var->type) == GLSL_TYPE_FLOAT)
+ var->type = glsl_float16_type(var->type);
+
+ return glsl_get_base_type(var->type) == GLSL_TYPE_FLOAT16;
+ }
+ }
+
+ return false;
+}
+
+static void
+lower_mediump_outputs(nir_shader *nir)
+{
+ nir_function_impl *impl = nir_shader_get_entrypoint(nir);
+ assert(impl);
+
+ /* Get rid of old derefs before we change the types of the variables */
+ nir_opt_dce(nir);
+
+ nir_builder b;
+ nir_builder_init(&b, impl);
+
+ nir_foreach_block_safe (block, impl) {
+ nir_foreach_instr_safe (instr, block) {
+ if (instr->type != nir_instr_type_intrinsic)
+ continue;
+
+ nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
+ if (intr->intrinsic != nir_intrinsic_store_output)
+ continue;
+
+ if (!lower_output_var(nir, nir_intrinsic_base(intr)))
+ continue;
+
+ b.cursor = nir_before_instr(&intr->instr);
+ nir_instr_rewrite_src(&intr->instr, &intr->src[0],
+ nir_src_for_ssa(nir_f2f16(&b, intr->src[0].ssa)));
+ }
+ }
+}
+
struct ir3_shader *
ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir)
{
struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
+ mtx_init(&shader->variants_lock, mtx_plain);
shader->compiler = compiler;
- shader->id = ++shader->compiler->shader_count;
+ shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
shader->type = nir->info.stage;
NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
(nir_lower_io_options)0);
+ if (compiler->gpu_id >= 600 &&
+ nir->info.stage == MESA_SHADER_FRAGMENT &&
+ !(ir3_shader_debug & IR3_DBG_NOFP16))
+ lower_mediump_outputs(nir);
+
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
/* NOTE: lower load_barycentric_at_sample first, since it
* produces load_barycentric_at_offset:
NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
+ NIR_PASS_V(nir, nir_lower_amul, ir3_glsl_type_size);
+
/* do first pass optimization, ignoring the key: */
- shader->nir = ir3_optimize_nir(shader, nir, NULL);
+ ir3_optimize_nir(shader, nir, NULL);
+
+ shader->nir = nir;
if (ir3_shader_debug & IR3_DBG_DISASM) {
printf("dump nir%d: type=%d", shader->id, shader->type);
nir_print_shader(shader->nir, stdout);
static void dump_reg(FILE *out, const char *name, uint32_t r)
{
- if (r != regid(63,0))
- fprintf(out, "; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
+ if (r != regid(63,0)) {
+ const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
+ fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
+ (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
+ }
}
static void dump_output(FILE *out, struct ir3_shader_variant *so,
dump_reg(out, name, regid);
}
+static const char *
+input_name(struct ir3_shader_variant *so, int i)
+{
+ if (so->inputs[i].sysval) {
+ return gl_system_value_name(so->inputs[i].slot);
+ } else if (so->type == MESA_SHADER_VERTEX) {
+ return gl_vert_attrib_name(so->inputs[i].slot);
+ } else {
+ return gl_varying_slot_name(so->inputs[i].slot);
+ }
+}
+
+static const char *
+output_name(struct ir3_shader_variant *so, int i)
+{
+ if (so->type == MESA_SHADER_FRAGMENT) {
+ return gl_frag_result_name(so->outputs[i].slot);
+ } else {
+ switch (so->outputs[i].slot) {
+ case VARYING_SLOT_GS_HEADER_IR3:
+ return "GS_HEADER";
+ case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
+ return "GS_VERTEX_FLAGS";
+ case VARYING_SLOT_TCS_HEADER_IR3:
+ return "TCS_HEADER";
+ default:
+ return gl_varying_slot_name(so->outputs[i].slot);
+ }
+ }
+}
+
void
ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
{
struct ir3 *ir = so->ir;
struct ir3_register *reg;
- const char *type = ir3_shader_stage(so->shader);
+ const char *type = ir3_shader_stage(so);
uint8_t regid;
unsigned i;
- for (i = 0; i < ir->ninputs; i++) {
- if (!ir->inputs[i]) {
- fprintf(out, "; in%d unused\n", i);
- continue;
- }
- reg = ir->inputs[i]->regs[0];
+ struct ir3_instruction *instr;
+ foreach_input_n (instr, i, ir) {
+ reg = instr->regs[0];
regid = reg->num;
- fprintf(out, "@in(%sr%d.%c)\tin%d\n",
+ fprintf(out, "@in(%sr%d.%c)\tin%d",
(reg->flags & IR3_REG_HALF) ? "h" : "",
(regid >> 2), "xyzw"[regid & 0x3], i);
+
+ if (reg->wrmask > 0x1)
+ fprintf(out, " (wrmask=0x%x)", reg->wrmask);
+ fprintf(out, "\n");
}
- for (i = 0; i < ir->noutputs; i++) {
- if (!ir->outputs[i]) {
- fprintf(out, "; out%d unused\n", i);
- continue;
- }
- /* kill shows up as a virtual output.. skip it! */
- if (is_kill(ir->outputs[i]))
- continue;
- reg = ir->outputs[i]->regs[0];
+ /* print pre-dispatch texture fetches: */
+ for (i = 0; i < so->num_sampler_prefetch; i++) {
+ const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
+ fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=%x, cmd=%u\n",
+ fetch->half_precision ? "h" : "",
+ fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
+ fetch->src, fetch->samp_id, fetch->tex_id,
+ fetch->wrmask, fetch->cmd);
+ }
+
+ foreach_output_n (instr, i, ir) {
+ reg = instr->regs[0];
regid = reg->num;
- fprintf(out, "@out(%sr%d.%c)\tout%d\n",
+ fprintf(out, "@out(%sr%d.%c)\tout%d",
(reg->flags & IR3_REG_HALF) ? "h" : "",
(regid >> 2), "xyzw"[regid & 0x3], i);
+ if (reg->wrmask > 0x1)
+ fprintf(out, " (wrmask=0x%x)", reg->wrmask);
+ fprintf(out, "\n");
}
- struct ir3_const_state *const_state = &so->const_state;
- for (i = 0; i < so->immediates_count; i++) {
+ struct ir3_const_state *const_state = &so->shader->const_state;
+ for (i = 0; i < const_state->immediates_count; i++) {
fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
- so->immediates[i].val[0],
- so->immediates[i].val[1],
- so->immediates[i].val[2],
- so->immediates[i].val[3]);
+ const_state->immediates[i].val[0],
+ const_state->immediates[i].val[1],
+ const_state->immediates[i].val[2],
+ const_state->immediates[i].val[3]);
}
disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
- switch (so->type) {
- case MESA_SHADER_VERTEX:
- fprintf(out, "; %s: outputs:", type);
- for (i = 0; i < so->outputs_count; i++) {
- uint8_t regid = so->outputs[i].regid;
- fprintf(out, " r%d.%c (%s)",
- (regid >> 2), "xyzw"[regid & 0x3],
- gl_varying_slot_name(so->outputs[i].slot));
- }
- fprintf(out, "\n");
- fprintf(out, "; %s: inputs:", type);
- for (i = 0; i < so->inputs_count; i++) {
- uint8_t regid = so->inputs[i].regid;
- fprintf(out, " r%d.%c (cm=%x,il=%u,b=%u)",
- (regid >> 2), "xyzw"[regid & 0x3],
- so->inputs[i].compmask,
- so->inputs[i].inloc,
- so->inputs[i].bary);
- }
- fprintf(out, "\n");
- break;
- case MESA_SHADER_FRAGMENT:
- fprintf(out, "; %s: outputs:", type);
- for (i = 0; i < so->outputs_count; i++) {
- uint8_t regid = so->outputs[i].regid;
- fprintf(out, " r%d.%c (%s)",
- (regid >> 2), "xyzw"[regid & 0x3],
- gl_frag_result_name(so->outputs[i].slot));
- }
- fprintf(out, "\n");
- fprintf(out, "; %s: inputs:", type);
- for (i = 0; i < so->inputs_count; i++) {
- uint8_t regid = so->inputs[i].regid;
- fprintf(out, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
- (regid >> 2), "xyzw"[regid & 0x3],
- gl_varying_slot_name(so->inputs[i].slot),
- so->inputs[i].compmask,
- so->inputs[i].inloc,
- so->inputs[i].bary);
- }
- fprintf(out, "\n");
- break;
- default:
- /* TODO */
- break;
+ fprintf(out, "; %s: outputs:", type);
+ for (i = 0; i < so->outputs_count; i++) {
+ uint8_t regid = so->outputs[i].regid;
+ const char *reg_type = so->outputs[i].half ? "hr" : "r";
+ fprintf(out, " %s%d.%c (%s)",
+ reg_type, (regid >> 2), "xyzw"[regid & 0x3],
+ output_name(so, i));
+ }
+ fprintf(out, "\n");
+
+ fprintf(out, "; %s: inputs:", type);
+ for (i = 0; i < so->inputs_count; i++) {
+ uint8_t regid = so->inputs[i].regid;
+ fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
+ (regid >> 2), "xyzw"[regid & 0x3],
+ input_name(so, i),
+ so->inputs[i].slot,
+ so->inputs[i].compmask,
+ so->inputs[i].inloc,
+ so->inputs[i].bary);
}
+ fprintf(out, "\n");
/* print generic shader info: */
- fprintf(out, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
+ fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u dwords\n",
type, so->shader->id, so->id,
so->info.instrs_count,
- so->info.max_half_reg + 1,
- so->info.max_reg + 1);
+ so->info.nops_count,
+ so->info.instrs_count - so->info.nops_count,
+ so->info.sizedwords);
- fprintf(out, "; %d const, %u constlen\n",
- so->info.max_const + 1,
+ fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
+ type, so->shader->id, so->id,
+ so->info.last_baryf,
+ so->info.max_half_reg + 1,
+ so->info.max_reg + 1,
so->constlen);
- fprintf(out, "; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
-
- fprintf(out, "; max_sun=%u\n", ir->max_sun);
+ fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
+ type, so->shader->id, so->id,
+ so->info.sstall,
+ so->info.ss,
+ so->info.sy,
+ so->max_sun,
+ so->loops);
/* print shader type specific info: */
switch (so->type) {
break;
case MESA_SHADER_FRAGMENT:
dump_reg(out, "pos (ij_pixel)",
- ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PIXEL));
+ ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
dump_reg(out, "pos (ij_centroid)",
- ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_CENTROID));
+ ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
dump_reg(out, "pos (ij_size)",
- ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_SIZE));
+ ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
if (so->color0_mrt) {
dump_output(out, so, FRAG_RESULT_COLOR, "color");
dump_output(out, so, FRAG_RESULT_DATA6, "data6");
dump_output(out, so, FRAG_RESULT_DATA7, "data7");
}
- /* these two are hard-coded since we don't know how to
- * program them to anything but all 0's...
- */
- if (so->frag_coord)
- fprintf(out, "; fragcoord: r0.x\n");
- if (so->frag_face)
- fprintf(out, "; fragface: hr0.x\n");
+ dump_reg(out, "fragcoord",
+ ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
+ dump_reg(out, "fragface",
+ ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
break;
default:
/* TODO */
projects / mesa.git / blobdiff