freedreno/a6xx: Document the bit for the magic 32bit-uniforms-as-16b mode.

[mesa.git] / src / freedreno / registers / adreno / a6xx.xml

diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 559f253f3a04f737c1c6921c996d3e3c3295e740..15314fbb7365c15ced9a219a9e590ead9cdc777a 100644 (file)
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -150,8 +150,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
        <value value="0xcd" name="FMT6_ASTC_12x10"/>
        <value value="0xce" name="FMT6_ASTC_12x12"/>
 
-       <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
-       <value value="0xea" name="FMT6_S8Z24_UINT"/>
+       <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
+       <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
 
        <!-- Not a hw enum, used internally in driver -->
        <value value="0xff" name="FMT6_NONE"/>
@@ -3325,7 +3325,17 @@ to upconvert to 32b float internally?
        <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
 
        <!-- always 0x5 ? -->
-       <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
+       <reg32 offset="0xab00" name="SP_MODE_CONTROL">
+         <!--
+         When set, half register loads from the constant file will
+         load a 32-bit value (so hc0.y loads the same value as c0.y)
+         and implicitly convert it to 16b (f2f16, or u2u16, based on
+         operand type).  When unset, half register loads from the
+         constant file will load 16 bits from the packed constant
+         file (so hc0.y loads the top 16 bits of the value of c0.x)
+         -->
+               <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
+       </reg32>
 
        <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
        <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>