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freedreno/a6xx: Document the bit for the magic 32bit-uniforms-as-16b mode.
authorEric Anholt <eric@anholt.net>
Wed, 8 Jul 2020 02:12:14 +0000 (19:12 -0700)
committerMarge Bot <eric+marge@anholt.net>
Wed, 5 Aug 2020 04:35:05 +0000 (04:35 +0000)
Trying to figure out how uniforms were working, I found that computerator
had different behavior from our GL fragment shaders.  Given that 3xx had
an SP_ bit for this (thanks flto@ for the note), it was a matter of
pasting bits of SP_* setup into computerator until I got the GL behavior.
I named it the same as the a3xx register.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6179>

src/freedreno/.gitlab-ci/reference/crash.log patch | blob | history
src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log patch | blob | history
src/freedreno/.gitlab-ci/reference/fd-clouds.log patch | blob | history
src/freedreno/registers/adreno/a6xx.xml patch | blob | history
src/freedreno/vulkan/tu_cmd_buffer.c patch | blob | history
src/gallium/drivers/freedreno/a6xx/fd6_emit.c patch | blob | history
src/gallium/drivers/freedreno/a6xx/fd6_program.c patch | blob | history

diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index 7f17459bf6395a96acb51c7b23f3fd3757315164..4cbc4e42bed45d4e21384b004261edd99e5d769b 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -7239,7 +7239,7 @@ clusters:
        deadbeef        HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 }
   - cluster-name: CLUSTER_SP_VS
     - context: 0
-       00000000        SP_UNKNOWN_AB00: 0
+       00000000        SP_MODE_CONTROL: { 0 }
        00000100        SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
        00000000        SP_FS_INSTRLEN: 0
        2764a40a        SP_BINDLESS_BASE[0].ADDR: 0x2764a40a
@@ -7256,7 +7256,7 @@ clusters:
        00013c40        SP_IBO_HI: 0x13c40
        00000040        SP_IBO_COUNT: 64
     - context: 1
-       00000000        SP_UNKNOWN_AB00: 0
+       00000000        SP_MODE_CONTROL: { 0 }
        00000100        SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
        00000000        SP_FS_INSTRLEN: 0
        2764a40a        SP_BINDLESS_BASE[0].ADDR: 0x2764a40a
@@ -7624,7 +7624,7 @@ clusters:
        00000000        HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0
   - cluster-name: CLUSTER_SP_PS
     - context: 0
-       00000000        SP_UNKNOWN_AB00: 0
+       00000000        SP_MODE_CONTROL: { 0 }
        00000100        SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
        00000000        SP_FS_INSTRLEN: 0
        cdb94116        SP_BINDLESS_BASE[0].ADDR: 0xcdb94116
@@ -7641,7 +7641,7 @@ clusters:
        00010202        SP_IBO_HI: 0x10202
        00000040        SP_IBO_COUNT: 64
     - context: 1
-       00000000        SP_UNKNOWN_AB00: 0
+       00000000        SP_MODE_CONTROL: { 0 }
        00000100        SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
        00000000        SP_FS_INSTRLEN: 0
        cdb94116        SP_BINDLESS_BASE[0].ADDR: 0xcdb94116
diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index 1115b3040d3f616f3b078890b21c9c7100ca5577..2471e5b9352e63fcdeadfd2229cdd0ab0f0a0a01 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -75,8 +75,8 @@ t4            write SP_UNKNOWN_A982 (a982)
 t4             write SP_UNKNOWN_A9A8 (a9a8)
                        SP_UNKNOWN_A9A8: 0
 00000000010580b4:              0000: 40a9a801 00000000
-t4             write SP_UNKNOWN_AB00 (ab00)
-                       SP_UNKNOWN_AB00: 0x5
+t4             write SP_MODE_CONTROL (ab00)
+                       SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
 00000000010580bc:              0000: 40ab0001 00000005
 t4             write VFD_ADD_OFFSET (a009)
                        VFD_ADD_OFFSET: { VERTEX }
@@ -345,7 +345,7 @@ t7          opcode: CP_BLIT (2c) (2 dwords)
  +     00000000                SP_GS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = TWO_QUADS }
  +     00000000                SP_UNKNOWN_A982: 0
  +     00000000                SP_UNKNOWN_A9A8: 0
-!+     00000005                SP_UNKNOWN_AB00: 0x5
+!+     00000005                SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
  +     00000000                SP_IBO_COUNT: 0
 !+     0000f180                SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
  +     00000000                SP_UNKNOWN_AE00: 0
diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index afb8e7f899d74c6a3c96286a19d67819cbe31333..949862982f057f29aebc86f3a33ef46e09582cc6 100644 (file)
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -66,8 +66,8 @@ t4            write UCHE_CLIENT_PF (0e19)
 t4             write RB_UNKNOWN_8E01 (8e01)
                        RB_UNKNOWN_8E01: 0x1
 0000000001d9109c:              0000: 408e0101 00000001
-t4             write SP_UNKNOWN_AB00 (ab00)
-                       SP_UNKNOWN_AB00: 0x5
+t4             write SP_MODE_CONTROL (ab00)
+                       SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
 0000000001d910a4:              0000: 40ab0001 00000005
 t4             write VFD_ADD_OFFSET (a009)
                        VFD_ADD_OFFSET: { VERTEX }
@@ -612,8 +612,8 @@ t4                                  write SP_FS_PREFETCH_CNTL (a99e)
 t4                                     write SP_UNKNOWN_A9A8 (a9a8)
                                                SP_UNKNOWN_A9A8: 0
 0000000001121010:                                      0000: 40a9a801 00000000
-t4                                     write SP_UNKNOWN_AB00 (ab00)
-                                               SP_UNKNOWN_AB00: 0x5
+t4                                     write SP_MODE_CONTROL (ab00)
+                                               SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
 0000000001121018:                                      0000: 40ab0001 00000005
 t4                                     write SP_FS_OUTPUT_CNTL0 (a98c)
                                                SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
@@ -1140,7 +1140,7 @@ t7                        opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 !+     00000031                        SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
 !+     00007fc0                        SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 }
  +     00000000                        SP_UNKNOWN_A9A8: 0
-!+     00000005                        SP_UNKNOWN_AB00: 0x5
+!+     00000005                        SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
 !+     00000100                        SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
  +     00000000                        SP_IBO_COUNT: 0
  +     00000000                        SP_UNKNOWN_AE00: 0
@@ -1927,8 +1927,8 @@ t4                                        write SP_FS_PREFETCH_CNTL (a99e)
 t4                                     write SP_UNKNOWN_A9A8 (a9a8)
                                                SP_UNKNOWN_A9A8: 0
 0000000001120010:                                      0000: 40a9a801 00000000
-t4                                     write SP_UNKNOWN_AB00 (ab00)
-                                               SP_UNKNOWN_AB00: 0x5
+t4                                     write SP_MODE_CONTROL (ab00)
+                                               SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
 0000000001120018:                                      0000: 40ab0001 00000005
 t4                                     write SP_FS_OUTPUT_CNTL0 (a98c)
                                                SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
@@ -6792,7 +6792,7 @@ t7                        opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
 !+     00000004                        SP_FS_OUTPUT[0x7].REG: { REGID = r1.x }
  +     00007fc0                        SP_FS_PREFETCH_CNTL: { COUNT = 0 | UNK4 = r63.x | 0x7000 }
  +     00000000                        SP_UNKNOWN_A9A8: 0
- +     00000005                        SP_UNKNOWN_AB00: 0x5
+ +     00000005                        SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
  +     00000100                        SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
 !+     00000058                        SP_FS_INSTRLEN: 88
 !+     011160a0                        SP_IBO_LO: 0x11160a0            base=1116000, offset=160, size=388
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 63653c2fb4547040602f186f45a3c22f111a8203..15314fbb7365c15ced9a219a9e590ead9cdc777a 100644 (file)
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -3325,7 +3325,17 @@ to upconvert to 32b float internally?
        <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
 
        <!-- always 0x5 ? -->
-       <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
+       <reg32 offset="0xab00" name="SP_MODE_CONTROL">
+         <!--
+         When set, half register loads from the constant file will
+         load a 32-bit value (so hc0.y loads the same value as c0.y)
+         and implicitly convert it to 16b (f2f16, or u2u16, based on
+         operand type).  When unset, half register loads from the
+         constant file will load 16 bits from the packed constant
+         file (so hc0.y loads the top 16 bits of the value of c0.x)
+         -->
+               <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
+       </reg32>
 
        <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
        <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 6d76f00f9e0c39e479a4ef86174739f0d051ec60..36d0e462edc24f1ae94e52c35dc42dc7fd931c5e 100644 (file)
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -824,7 +824,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
    tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01, 0x0);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A982, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
-   tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
+   tu_cs_emit_write_reg(cs, REG_A6XX_SP_MODE_CONTROL,
+                        A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
 
    /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
    tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 2d502032bfa9668c4c333c13bac04520917adb58..67d9a8f13ae7b8099ac243d18b028b2bbd6cc7e5 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1174,7 +1174,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
        WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
        WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
        WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
-       WRITE(REG_A6XX_SP_UNKNOWN_AB00, 0x5);
+       WRITE(REG_A6XX_SP_MODE_CONTROL, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
        WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
        WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
        WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 973086ddd00cd8436ef7fdf171910e59bbb62cac..7d57b2d1b5d120aa7011ba3cc407561901789812 100644 (file)
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -434,8 +434,8 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
        OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
        OUT_RING(ring, 0);
 
-       OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
-       OUT_RING(ring, 0x5);
+       OUT_PKT4(ring, REG_A6XX_SP_MODE_CONTROL, 1);
+       OUT_RING(ring, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
 
        OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
        OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |