return VK_SUCCESS;
}
+static bool
+is_linear_mipmapped(const struct tu_image_view *iview)
+{
+ return iview->image->layout.tile_mode == TILE6_LINEAR &&
+ iview->base_mip != iview->image->level_count - 1;
+}
+
+static bool
+force_sysmem(const struct tu_cmd_buffer *cmd,
+ const struct VkRect2D *render_area)
+{
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+ const struct tu_physical_device *device = cmd->device->physical_device;
+ bool has_linear_mipmapped_store = false;
+ const struct tu_render_pass *pass = cmd->state.pass;
+
+ /* Iterate over all the places we call tu6_emit_store_attachment() */
+ for (unsigned i = 0; i < pass->subpass_count; i++) {
+ const struct tu_subpass *subpass = &pass->subpasses[i];
+ if (subpass->resolve_attachments) {
+ for (unsigned i = 0; i < subpass->color_count; i++) {
+ uint32_t a = subpass->resolve_attachments[i].attachment;
+ if (a != VK_ATTACHMENT_UNUSED &&
+ cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
+ const struct tu_image_view *iview = fb->attachments[a].attachment;
+ if (is_linear_mipmapped(iview)) {
+ has_linear_mipmapped_store = true;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ for (unsigned i = 0; i < pass->attachment_count; i++) {
+ if (pass->attachments[i].gmem_offset >= 0 &&
+ cmd->state.pass->attachments[i].store_op == VK_ATTACHMENT_STORE_OP_STORE) {
+ const struct tu_image_view *iview = fb->attachments[i].attachment;
+ if (is_linear_mipmapped(iview)) {
+ has_linear_mipmapped_store = true;
+ break;
+ }
+ }
+ }
+
+ /* Linear textures cannot have any padding between mipmap levels and their
+ * height isn't padded, while at the same time the GMEM->MEM resolve does
+ * not have per-pixel granularity, so if the image height isn't aligned to
+ * the resolve granularity and the render area is tall enough, we may wind
+ * up writing past the bottom of the image into the next miplevel or even
+ * past the end of the image. For the last miplevel, the layout code should
+ * insert enough padding so that the overdraw writes to the padding. To
+ * work around this, we force-enable sysmem rendering.
+ */
+ const uint32_t y2 = render_area->offset.y + render_area->extent.height;
+ const uint32_t aligned_y2 = ALIGN_POT(y2, device->tile_align_h);
+
+ return has_linear_mipmapped_store && aligned_y2 > fb->height;
+}
+
static void
tu_tiling_config_update_tile_layout(struct tu_tiling_config *tiling,
const struct tu_device *dev,
if (unlikely(cmd->device->physical_device->instance->debug_flags & TU_DEBUG_SYSMEM))
return true;
- return false;
+ return cmd->state.tiling_config.force_sysmem;
}
static void
const struct tu_tile *tile)
{
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
- tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x7));
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD));
tu6_emit_marker(cmd, cs);
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
- tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
tu6_emit_marker(cmd, cs);
const uint32_t x1 = tile->begin.x;
&info->pClearValues[a]);
}
+static void
+tu6_emit_predicated_blit(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t a,
+ uint32_t gmem_a,
+ bool resolve)
+{
+ const uint32_t space = 14 + 6;
+ struct tu_cond_exec_state state;
+
+ VkResult result = tu_cond_exec_start(cmd->device, cs, &state,
+ CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
+ CP_COND_REG_EXEC_0_GMEM,
+ space);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
+
+ tu6_emit_blit_info(cmd, cs,
+ cmd->state.framebuffer->attachments[a].attachment,
+ cmd->state.pass->attachments[gmem_a].gmem_offset, resolve);
+ tu6_emit_blit(cmd, cs);
+
+ tu_cond_exec_end(cs, &state);
+}
+
+static void
+tu6_emit_sysmem_resolve(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t a,
+ uint32_t gmem_a)
+{
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+ const struct tu_image_view *dst = fb->attachments[a].attachment;
+ const struct tu_image_view *src = fb->attachments[gmem_a].attachment;
+
+ tu_blit(cmd, cs, &(struct tu_blit) {
+ .dst = sysmem_attachment_surf(dst, dst->base_layer,
+ &cmd->state.tiling_config.render_area),
+ .src = sysmem_attachment_surf(src, src->base_layer,
+ &cmd->state.tiling_config.render_area),
+ .layers = fb->layers,
+ });
+}
+
+
+/* Emit a MSAA resolve operation, with both gmem and sysmem paths. */
+static void tu6_emit_resolve(struct tu_cmd_buffer *cmd,
+ struct tu_cs *cs,
+ uint32_t a,
+ uint32_t gmem_a)
+{
+ if (cmd->state.pass->attachments[a].store_op == VK_ATTACHMENT_STORE_OP_DONT_CARE)
+ return;
+
+ tu6_emit_predicated_blit(cmd, cs, a, gmem_a, true);
+
+ const struct tu_framebuffer *fb = cmd->state.framebuffer;
+ const uint32_t space = 25 + 66 * fb->layers + 17;
+ struct tu_cond_exec_state state;
+
+ VkResult result = tu_cond_exec_start(cmd->device, cs, &state,
+ CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
+ CP_COND_REG_EXEC_0_SYSMEM,
+ space);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
+
+ tu6_emit_sysmem_resolve(cmd, cs, a, gmem_a);
+ tu_cond_exec_end(cs, &state);
+}
+
static void
tu6_emit_store_attachment(struct tu_cmd_buffer *cmd,
struct tu_cs *cs,
tu6_emit_marker(cmd, cs);
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
- tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
tu6_emit_marker(cmd, cs);
tu6_emit_blit_scissor(cmd, cs, true);
* when nothing clears which we currently can't handle.
*/
tu_cs_reserve_space(cmd->device, &sub_cs, 5);
- tu6_emit_event_write(cmd, &sub_cs, UNK_1D, true);
+ tu6_emit_event_write(cmd, &sub_cs, PC_CCU_FLUSH_COLOR_TS, true);
cmd->state.sysmem_clear_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
}
tu6_emit_marker(cmd, cs);
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
- tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10);
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
tu6_emit_marker(cmd, cs);
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
static void
tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
+ /* Do any resolves of the last subpass. These are handled in the
+ * tile_store_ib in the gmem path.
+ */
+
+ const struct tu_subpass *subpass = cmd->state.subpass;
+ if (subpass->resolve_attachments) {
+ for (unsigned i = 0; i < subpass->color_count; i++) {
+ uint32_t a = subpass->resolve_attachments[i].attachment;
+ if (a != VK_ATTACHMENT_UNUSED)
+ tu6_emit_sysmem_resolve(cmd, cs, a,
+ subpass->color_attachments[i].attachment);
+ }
+ }
+
const uint32_t space = 14 + tu_cs_get_call_size(&cmd->draw_epilogue_cs);
VkResult result = tu_cs_reserve_space(cmd->device, cs, space);
if (result != VK_SUCCESS) {
tu6_emit_lrz_flush(cmd, cs);
- tu6_emit_event_write(cmd, cs, UNK_1C, true);
- tu6_emit_event_write(cmd, cs, UNK_1D, true);
+ tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
+ tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
tu_cs_sanity_check(cs);
}
/* if (no overflow) */ {
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
- tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
}
}
struct tu_tiling_config *tiling = &cmd->state.tiling_config;
tiling->render_area = *render_area;
+ tiling->force_sysmem = force_sysmem(cmd, render_area);
tu_tiling_config_update_tile_layout(tiling, dev, cmd->state.pass->gmem_pixels);
tu_tiling_config_update_pipe_layout(tiling, dev);
const struct tu_render_pass *pass = cmd->state.pass;
struct tu_cs *cs = &cmd->draw_cs;
- VkResult result = tu_cs_reserve_space(cmd->device, cs, 1024);
- if (result != VK_SUCCESS) {
- cmd->record_result = result;
- return;
- }
-
const struct tu_subpass *subpass = cmd->state.subpass++;
/* TODO:
* if msaa samples change between subpasses,
for (unsigned i = 0; i < subpass->color_count; i++) {
uint32_t a = subpass->resolve_attachments[i].attachment;
if (a != VK_ATTACHMENT_UNUSED) {
- tu6_emit_store_attachment(cmd, cs, a,
- subpass->color_attachments[i].attachment);
+ tu6_emit_resolve(cmd, cs, a,
+ subpass->color_attachments[i].attachment);
}
}
}
+ VkResult result = tu_cs_reserve_space(cmd->device, &cmd->draw_cs, 1024);
+ if (result != VK_SUCCESS) {
+ cmd->record_result = result;
+ return;
+ }
+
/* invalidate because reading input attachments will cache GMEM and
* the cache isn''t updated when GMEM is written
* TODO: is there a no-cache bit for textures?
/* Emit flushes so that input attachments will read the correct value. This
* is for sysmem only, although it shouldn't do much harm on gmem.
*/
- tu6_emit_event_write(cmd, cs, UNK_1C, true);
- tu6_emit_event_write(cmd, cs, UNK_1D, true);
+ tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
+ tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
/* TODO:
* since we don't know how to do GMEM->GMEM resolve,
if (subpass->resolve_attachments) {
for (unsigned i = 0; i < subpass->color_count; i++) {
uint32_t a = subpass->resolve_attachments[i].attachment;
- const struct tu_image_view *iview =
- cmd->state.framebuffer->attachments[a].attachment;
if (a != VK_ATTACHMENT_UNUSED && pass->attachments[a].gmem_offset >= 0) {
tu_finishme("missing GMEM->GMEM resolve, performance will suffer\n");
- tu6_emit_blit_info(cmd, cs, iview, pass->attachments[a].gmem_offset, false);
- tu6_emit_blit(cmd, cs);
+ tu6_emit_predicated_blit(cmd, cs, a, a, false);
}
}
}
TU_DRAW_STATE_VS_CONST,
TU_DRAW_STATE_FS_CONST,
TU_DRAW_STATE_VS_TEX,
- TU_DRAW_STATE_FS_TEX,
+ TU_DRAW_STATE_FS_TEX_SYSMEM,
+ TU_DRAW_STATE_FS_TEX_GMEM,
TU_DRAW_STATE_FS_IBO,
TU_DRAW_STATE_VS_PARAMS,
uint32_t *dst,
struct tu_descriptor_state *descriptors_state,
const struct tu_descriptor_map *map,
- unsigned i, unsigned array_index)
+ unsigned i, unsigned array_index, bool is_sysmem)
{
assert(descriptors_state->valid & (1 << map->set[i]));
break;
}
- if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT) {
+ if (layout->type == VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT && !is_sysmem) {
const struct tu_tiling_config *tiling = &cmd->state.tiling_config;
uint32_t a = cmd->state.subpass->input_attachments[map->value[i] +
array_index].attachment;
struct tu_descriptor_state *descriptors_state,
gl_shader_stage type,
struct tu_cs_entry *entry,
- bool *needs_border)
+ bool *needs_border,
+ bool is_sysmem)
{
struct tu_device *device = cmd->device;
struct tu_cs *draw_state = &cmd->sub_cs;
for (int j = 0; j < link->texture_map.array_size[i]; j++) {
write_tex_const(cmd,
&tex_const.map[A6XX_TEX_CONST_DWORDS * tex_index++],
- descriptors_state, &link->texture_map, i, j);
+ descriptors_state, &link->texture_map, i, j,
+ is_sysmem);
}
}
if (cmd->state.dirty &
(TU_CMD_DIRTY_PIPELINE | TU_CMD_DIRTY_DESCRIPTOR_SETS)) {
bool needs_border = false;
- struct tu_cs_entry vs_tex, fs_tex, fs_ibo;
+ struct tu_cs_entry vs_tex, fs_tex_sysmem, fs_tex_gmem, fs_ibo;
+
+ result = tu6_emit_textures(cmd, pipeline, descriptors_state,
+ MESA_SHADER_VERTEX, &vs_tex, &needs_border,
+ false);
+ if (result != VK_SUCCESS)
+ return result;
+ /* TODO: we could emit just one texture descriptor draw state when there
+ * are no input attachments, which is the most common case. We could
+ * also split out the sampler state, which doesn't change even for input
+ * attachments.
+ */
result = tu6_emit_textures(cmd, pipeline, descriptors_state,
- MESA_SHADER_VERTEX, &vs_tex, &needs_border);
+ MESA_SHADER_FRAGMENT, &fs_tex_sysmem,
+ &needs_border, true);
if (result != VK_SUCCESS)
return result;
result = tu6_emit_textures(cmd, pipeline, descriptors_state,
- MESA_SHADER_FRAGMENT, &fs_tex, &needs_border);
+ MESA_SHADER_FRAGMENT, &fs_tex_gmem,
+ &needs_border, false);
if (result != VK_SUCCESS)
return result;
};
draw_state_groups[draw_state_group_count++] =
(struct tu_draw_state_group) {
- .id = TU_DRAW_STATE_FS_TEX,
- .enable_mask = ENABLE_DRAW,
- .ib = fs_tex,
+ .id = TU_DRAW_STATE_FS_TEX_GMEM,
+ .enable_mask = CP_SET_DRAW_STATE__0_GMEM,
+ .ib = fs_tex_gmem,
+ };
+ draw_state_groups[draw_state_group_count++] =
+ (struct tu_draw_state_group) {
+ .id = TU_DRAW_STATE_FS_TEX_SYSMEM,
+ .enable_mask = CP_SET_DRAW_STATE__0_SYSMEM,
+ .ib = fs_tex_sysmem,
};
draw_state_groups[draw_state_group_count++] =
(struct tu_draw_state_group) {
bool needs_border;
result = tu6_emit_textures(cmd, pipeline, descriptors_state,
- MESA_SHADER_COMPUTE, &ib, &needs_border);
+ MESA_SHADER_COMPUTE, &ib, &needs_border, false);
if (result != VK_SUCCESS) {
cmd->record_result = result;
return;
cmd->state.dirty = TU_CMD_DIRTY_PIPELINE;
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
- tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(0x8));
+ tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE));
const uint32_t *local_size = pipeline->compute.local_size;
const uint32_t *num_groups = info->blocks;
projects / mesa.git / blobdiff