* DEALINGS IN THE SOFTWARE.
*/
+#include "common/freedreno_guardband.h"
#include "tu_private.h"
#include "ir3/ir3_nir.h"
#include "tu_cs.h"
-uint32_t
-tu6_stage2opcode(gl_shader_stage stage)
-{
- if (stage == MESA_SHADER_FRAGMENT || stage == MESA_SHADER_COMPUTE)
- return CP_LOAD_STATE6_FRAG;
- return CP_LOAD_STATE6_GEOM;
-}
-
-static enum a6xx_state_block
-tu6_stage2texsb(gl_shader_stage stage)
-{
- return SB6_VS_TEX + stage;
-}
-
-enum a6xx_state_block
-tu6_stage2shadersb(gl_shader_stage stage)
-{
- return SB6_VS_SHADER + stage;
-}
-
/* Emit IB that preloads the descriptors that the shader uses */
static void
}
static unsigned
-tu6_load_state_size(struct tu_pipeline_layout *layout, bool compute)
+tu6_load_state_size(struct tu_pipeline *pipeline, bool compute)
{
const unsigned load_state_size = 4;
unsigned size = 0;
- for (unsigned i = 0; i < layout->num_sets; i++) {
- struct tu_descriptor_set_layout *set_layout = layout->set[i].layout;
+ for (unsigned i = 0; i < pipeline->layout->num_sets; i++) {
+ if (pipeline && !(pipeline->active_desc_sets & (1u << i)))
+ continue;
+
+ struct tu_descriptor_set_layout *set_layout = pipeline->layout->set[i].layout;
for (unsigned j = 0; j < set_layout->binding_count; j++) {
struct tu_descriptor_set_binding_layout *binding = &set_layout->binding[j];
unsigned count = 0;
binding->shader_stages & VK_SHADER_STAGE_COMPUTE_BIT :
binding->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
unsigned stage_count = util_bitcount(stages);
+
+ if (!binding->array_size)
+ continue;
+
switch (binding->type) {
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
case VK_DESCRIPTOR_TYPE_SAMPLER:
case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
- case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
/* Textures and UBO's needs a packet for each stage */
*/
count = stage_count * binding->array_size * 2;
break;
+ case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
+ break;
default:
unreachable("bad descriptor type");
}
static void
tu6_emit_load_state(struct tu_pipeline *pipeline, bool compute)
{
- unsigned size = tu6_load_state_size(pipeline->layout, compute);
+ unsigned size = tu6_load_state_size(pipeline, compute);
if (size == 0)
return;
}
}
- pipeline->load_state.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
+ pipeline->load_state = tu_cs_end_draw_state(&pipeline->cs, &cs);
}
struct tu_pipeline_builder
struct tu_shader *shaders[MESA_SHADER_STAGES];
struct ir3_shader_variant *variants[MESA_SHADER_STAGES];
struct ir3_shader_variant *binning_variant;
- uint32_t shader_offsets[MESA_SHADER_STAGES];
- uint32_t binning_vs_offset;
- uint32_t shader_total_size;
+ uint64_t shader_iova[MESA_SHADER_STAGES];
+ uint64_t binning_vs_iova;
bool rasterizer_discard;
/* these states are affectd by rasterizer_discard */
return false;
}
-static enum pc_di_primtype
-tu6_primtype(VkPrimitiveTopology topology)
-{
- switch (topology) {
- case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
- return DI_PT_POINTLIST;
- case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
- return DI_PT_LINELIST;
- case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
- return DI_PT_LINESTRIP;
- case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
- return DI_PT_TRILIST;
- case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
- return DI_PT_TRISTRIP;
- case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
- return DI_PT_TRIFAN;
- case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
- return DI_PT_LINE_ADJ;
- case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
- return DI_PT_LINESTRIP_ADJ;
- case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
- return DI_PT_TRI_ADJ;
- case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
- return DI_PT_TRISTRIP_ADJ;
- case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
- default:
- unreachable("invalid primitive topology");
- return DI_PT_NONE;
- }
-}
-
-static enum adreno_compare_func
-tu6_compare_func(VkCompareOp op)
-{
- switch (op) {
- case VK_COMPARE_OP_NEVER:
- return FUNC_NEVER;
- case VK_COMPARE_OP_LESS:
- return FUNC_LESS;
- case VK_COMPARE_OP_EQUAL:
- return FUNC_EQUAL;
- case VK_COMPARE_OP_LESS_OR_EQUAL:
- return FUNC_LEQUAL;
- case VK_COMPARE_OP_GREATER:
- return FUNC_GREATER;
- case VK_COMPARE_OP_NOT_EQUAL:
- return FUNC_NOTEQUAL;
- case VK_COMPARE_OP_GREATER_OR_EQUAL:
- return FUNC_GEQUAL;
- case VK_COMPARE_OP_ALWAYS:
- return FUNC_ALWAYS;
- default:
- unreachable("invalid VkCompareOp");
- return FUNC_NEVER;
- }
-}
-
-static enum adreno_stencil_op
-tu6_stencil_op(VkStencilOp op)
-{
- switch (op) {
- case VK_STENCIL_OP_KEEP:
- return STENCIL_KEEP;
- case VK_STENCIL_OP_ZERO:
- return STENCIL_ZERO;
- case VK_STENCIL_OP_REPLACE:
- return STENCIL_REPLACE;
- case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
- return STENCIL_INCR_CLAMP;
- case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
- return STENCIL_DECR_CLAMP;
- case VK_STENCIL_OP_INVERT:
- return STENCIL_INVERT;
- case VK_STENCIL_OP_INCREMENT_AND_WRAP:
- return STENCIL_INCR_WRAP;
- case VK_STENCIL_OP_DECREMENT_AND_WRAP:
- return STENCIL_DECR_WRAP;
- default:
- unreachable("invalid VkStencilOp");
- return STENCIL_KEEP;
- }
-}
-
-static enum a3xx_rop_code
-tu6_rop(VkLogicOp op)
-{
- switch (op) {
- case VK_LOGIC_OP_CLEAR:
- return ROP_CLEAR;
- case VK_LOGIC_OP_AND:
- return ROP_AND;
- case VK_LOGIC_OP_AND_REVERSE:
- return ROP_AND_REVERSE;
- case VK_LOGIC_OP_COPY:
- return ROP_COPY;
- case VK_LOGIC_OP_AND_INVERTED:
- return ROP_AND_INVERTED;
- case VK_LOGIC_OP_NO_OP:
- return ROP_NOOP;
- case VK_LOGIC_OP_XOR:
- return ROP_XOR;
- case VK_LOGIC_OP_OR:
- return ROP_OR;
- case VK_LOGIC_OP_NOR:
- return ROP_NOR;
- case VK_LOGIC_OP_EQUIVALENT:
- return ROP_EQUIV;
- case VK_LOGIC_OP_INVERT:
- return ROP_INVERT;
- case VK_LOGIC_OP_OR_REVERSE:
- return ROP_OR_REVERSE;
- case VK_LOGIC_OP_COPY_INVERTED:
- return ROP_COPY_INVERTED;
- case VK_LOGIC_OP_OR_INVERTED:
- return ROP_OR_INVERTED;
- case VK_LOGIC_OP_NAND:
- return ROP_NAND;
- case VK_LOGIC_OP_SET:
- return ROP_SET;
- default:
- unreachable("invalid VkLogicOp");
- return ROP_NOOP;
- }
-}
-
-static enum adreno_rb_blend_factor
-tu6_blend_factor(VkBlendFactor factor)
-{
- switch (factor) {
- case VK_BLEND_FACTOR_ZERO:
- return FACTOR_ZERO;
- case VK_BLEND_FACTOR_ONE:
- return FACTOR_ONE;
- case VK_BLEND_FACTOR_SRC_COLOR:
- return FACTOR_SRC_COLOR;
- case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
- return FACTOR_ONE_MINUS_SRC_COLOR;
- case VK_BLEND_FACTOR_DST_COLOR:
- return FACTOR_DST_COLOR;
- case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
- return FACTOR_ONE_MINUS_DST_COLOR;
- case VK_BLEND_FACTOR_SRC_ALPHA:
- return FACTOR_SRC_ALPHA;
- case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
- return FACTOR_ONE_MINUS_SRC_ALPHA;
- case VK_BLEND_FACTOR_DST_ALPHA:
- return FACTOR_DST_ALPHA;
- case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
- return FACTOR_ONE_MINUS_DST_ALPHA;
- case VK_BLEND_FACTOR_CONSTANT_COLOR:
- return FACTOR_CONSTANT_COLOR;
- case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
- return FACTOR_ONE_MINUS_CONSTANT_COLOR;
- case VK_BLEND_FACTOR_CONSTANT_ALPHA:
- return FACTOR_CONSTANT_ALPHA;
- case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
- return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
- case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
- return FACTOR_SRC_ALPHA_SATURATE;
- case VK_BLEND_FACTOR_SRC1_COLOR:
- return FACTOR_SRC1_COLOR;
- case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
- return FACTOR_ONE_MINUS_SRC1_COLOR;
- case VK_BLEND_FACTOR_SRC1_ALPHA:
- return FACTOR_SRC1_ALPHA;
- case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
- return FACTOR_ONE_MINUS_SRC1_ALPHA;
- default:
- unreachable("invalid VkBlendFactor");
- return FACTOR_ZERO;
- }
-}
-
-static enum a3xx_rb_blend_opcode
-tu6_blend_op(VkBlendOp op)
-{
- switch (op) {
- case VK_BLEND_OP_ADD:
- return BLEND_DST_PLUS_SRC;
- case VK_BLEND_OP_SUBTRACT:
- return BLEND_SRC_MINUS_DST;
- case VK_BLEND_OP_REVERSE_SUBTRACT:
- return BLEND_DST_MINUS_SRC;
- case VK_BLEND_OP_MIN:
- return BLEND_MIN_DST_SRC;
- case VK_BLEND_OP_MAX:
- return BLEND_MAX_DST_SRC;
- default:
- unreachable("invalid VkBlendOp");
- return BLEND_DST_PLUS_SRC;
- }
-}
-
void
tu6_emit_xs_config(struct tu_cs *cs,
gl_shader_stage stage, /* xs->type, but xs may be NULL */
tu_cs_emit(cs, xs->instrlen);
tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
- tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs->constlen, 4)) |
+ tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
A6XX_HLSQ_VS_CNTL_ENABLED);
/* emit program binary
/* emit immediates */
- const struct ir3_const_state *const_state = &xs->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(xs);
uint32_t base = const_state->offsets.immediate;
- int size = const_state->immediates_count;
+ int size = DIV_ROUND_UP(const_state->immediates_count, 4);
/* truncate size to avoid writing constants that shader
* does not use:
tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
- for (unsigned i = 0; i < size; i++) {
- tu_cs_emit(cs, const_state->immediates[i].val[0]);
- tu_cs_emit(cs, const_state->immediates[i].val[1]);
- tu_cs_emit(cs, const_state->immediates[i].val[2]);
- tu_cs_emit(cs, const_state->immediates[i].val[3]);
- }
+ tu_cs_emit_array(cs, const_state->immediates, size * 4);
}
static void
const struct ir3_shader_variant *v,
uint32_t binary_iova)
{
- tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
- tu_cs_emit(cs, 0xff);
+ tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
+ .cs_state = true,
+ .cs_ibo = true));
tu6_emit_xs_config(cs, MESA_SHADER_COMPUTE, v, binary_iova);
static void
tu6_emit_vs_system_values(struct tu_cs *cs,
const struct ir3_shader_variant *vs,
+ const struct ir3_shader_variant *hs,
+ const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
bool primid_passthru)
{
ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
const uint32_t instanceid_regid =
ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
+ const uint32_t tess_coord_x_regid = hs ?
+ ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) :
+ regid(63, 0);
+ const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ?
+ tess_coord_x_regid + 1 :
+ regid(63, 0);
+ const uint32_t hs_patch_regid = hs ?
+ ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
+ regid(63, 0);
+ const uint32_t ds_patch_regid = hs ?
+ ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) :
+ regid(63, 0);
+ const uint32_t hs_invocation_regid = hs ?
+ ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
+ regid(63, 0);
const uint32_t primitiveid_regid = gs ?
ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) :
regid(63, 0);
A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) |
0xfc000000);
- tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */
- tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */
+ tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
+ A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
+ tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
+ A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
+ A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
+ 0xfc);
tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
0xfc00); /* VFD_CONTROL_5 */
}
static void
-tu6_setup_streamout(const struct ir3_shader_variant *v,
- struct ir3_shader_linkage *l, struct tu_streamout_state *tf)
+tu6_setup_streamout(struct tu_cs *cs,
+ const struct ir3_shader_variant *v,
+ struct ir3_shader_linkage *l)
{
const struct ir3_stream_output_info *info = &v->shader->stream_output;
+ uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {};
+ uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {};
+ uint32_t prog_count = align(l->max_loc, 2) / 2;
- memset(tf, 0, sizeof(*tf));
+ /* TODO: streamout state should be in a non-GMEM draw state */
- tf->prog_count = align(l->max_loc, 2) / 2;
-
- debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
+ /* no streamout: */
+ if (info->num_outputs == 0) {
+ tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4);
+ tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
+ tu_cs_emit(cs, 0);
+ tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
+ tu_cs_emit(cs, 0);
+ return;
+ }
- /* set stride info to the streamout state */
- for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++)
- tf->stride[i] = info->stride[i];
+ /* is there something to do with info->stride[i]? */
for (unsigned i = 0; i < info->num_outputs; i++) {
const struct ir3_stream_output *out = &info->output[i];
if (v->outputs[k].regid == INVALID_REG)
continue;
- tf->ncomp[out->output_buffer] += out->num_components;
+ ncomp[out->output_buffer] += out->num_components;
/* linkage map sorted by order frag shader wants things, so
* a bit less ideal here..
unsigned off = j + out->dst_offset; /* in dwords */
if (loc & 1) {
- tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
- A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
- A6XX_VPC_SO_PROG_B_OFF(off * 4);
+ prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
+ A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
+ A6XX_VPC_SO_PROG_B_OFF(off * 4);
} else {
- tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
- A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
- A6XX_VPC_SO_PROG_A_OFF(off * 4);
+ prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
+ A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
+ A6XX_VPC_SO_PROG_A_OFF(off * 4);
}
}
}
- tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
- COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
- COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
- COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
- COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
+ tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count);
+ tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL);
+ tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE |
+ COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
+ COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
+ COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
+ COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
+ for (uint32_t i = 0; i < 4; i++) {
+ tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i));
+ tu_cs_emit(cs, ncomp[i]);
+ }
+ /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */
+ tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
+ tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE);
+ for (uint32_t i = 0; i < prog_count; i++) {
+ tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
+ tu_cs_emit(cs, prog[i]);
+ }
}
static void
static void
tu6_emit_link_map(struct tu_cs *cs,
const struct ir3_shader_variant *producer,
- const struct ir3_shader_variant *consumer) {
- const struct ir3_const_state *const_state = &consumer->shader->const_state;
+ const struct ir3_shader_variant *consumer,
+ enum a6xx_state_block sb)
+{
+ const struct ir3_const_state *const_state = ir3_const_state(consumer);
uint32_t base = const_state->offsets.primitive_map;
uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
if (size <= 0)
return;
- tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size,
- patch_locs);
+ tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size,
+ patch_locs);
}
static uint16_t
void
tu6_emit_vpc(struct tu_cs *cs,
const struct ir3_shader_variant *vs,
+ const struct ir3_shader_variant *hs,
+ const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
const struct ir3_shader_variant *fs,
- struct tu_streamout_state *tf)
-{
- const struct ir3_shader_variant *last_shader = gs ?: vs;
+ uint32_t patch_control_points,
+ bool vshs_workgroup)
+{
+ /* note: doesn't compile as static because of the array regs.. */
+ const struct reg_config {
+ uint16_t reg_sp_xs_out_reg;
+ uint16_t reg_sp_xs_vpc_dst_reg;
+ uint16_t reg_vpc_xs_pack;
+ uint16_t reg_vpc_xs_clip_cntl;
+ uint16_t reg_gras_xs_cl_cntl;
+ uint16_t reg_pc_xs_out_cntl;
+ uint16_t reg_sp_xs_primitive_cntl;
+ uint16_t reg_vpc_xs_layer_cntl;
+ uint16_t reg_gras_xs_layer_cntl;
+ } reg_config[] = {
+ [MESA_SHADER_VERTEX] = {
+ REG_A6XX_SP_VS_OUT_REG(0),
+ REG_A6XX_SP_VS_VPC_DST_REG(0),
+ REG_A6XX_VPC_VS_PACK,
+ REG_A6XX_VPC_VS_CLIP_CNTL,
+ REG_A6XX_GRAS_VS_CL_CNTL,
+ REG_A6XX_PC_VS_OUT_CNTL,
+ REG_A6XX_SP_VS_PRIMITIVE_CNTL,
+ REG_A6XX_VPC_VS_LAYER_CNTL,
+ REG_A6XX_GRAS_VS_LAYER_CNTL
+ },
+ [MESA_SHADER_TESS_EVAL] = {
+ REG_A6XX_SP_DS_OUT_REG(0),
+ REG_A6XX_SP_DS_VPC_DST_REG(0),
+ REG_A6XX_VPC_DS_PACK,
+ REG_A6XX_VPC_DS_CLIP_CNTL,
+ REG_A6XX_GRAS_DS_CL_CNTL,
+ REG_A6XX_PC_DS_OUT_CNTL,
+ REG_A6XX_SP_DS_PRIMITIVE_CNTL,
+ REG_A6XX_VPC_DS_LAYER_CNTL,
+ REG_A6XX_GRAS_DS_LAYER_CNTL
+ },
+ [MESA_SHADER_GEOMETRY] = {
+ REG_A6XX_SP_GS_OUT_REG(0),
+ REG_A6XX_SP_GS_VPC_DST_REG(0),
+ REG_A6XX_VPC_GS_PACK,
+ REG_A6XX_VPC_GS_CLIP_CNTL,
+ REG_A6XX_GRAS_GS_CL_CNTL,
+ REG_A6XX_PC_GS_OUT_CNTL,
+ REG_A6XX_SP_GS_PRIMITIVE_CNTL,
+ REG_A6XX_VPC_GS_LAYER_CNTL,
+ REG_A6XX_GRAS_GS_LAYER_CNTL
+ },
+ };
+
+ const struct ir3_shader_variant *last_shader;
+ if (gs) {
+ last_shader = gs;
+ } else if (hs) {
+ last_shader = ds;
+ } else {
+ last_shader = vs;
+ }
+
+ const struct reg_config *cfg = ®_config[last_shader->type];
+
struct ir3_shader_linkage linkage = { .primid_loc = 0xff };
if (fs)
ir3_link_shaders(&linkage, last_shader, fs, true);
* passthrough needs to be enabled.
*/
bool primid_passthru = linkage.primid_loc != 0xff;
- tu6_emit_vs_system_values(cs, vs, gs, primid_passthru);
+ tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
tu_cs_emit(cs, ~linkage.varmask[0]);
ir3_find_output_regid(last_shader, VARYING_SLOT_POS);
const uint32_t pointsize_regid =
ir3_find_output_regid(last_shader, VARYING_SLOT_PSIZ);
- const uint32_t layer_regid = gs ?
- ir3_find_output_regid(gs, VARYING_SLOT_LAYER) : regid(63, 0);
+ const uint32_t layer_regid =
+ ir3_find_output_regid(last_shader, VARYING_SLOT_LAYER);
+ uint32_t primitive_regid = gs ?
+ ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0);
+ uint32_t flags_regid = gs ?
+ ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3) : 0;
uint32_t pointsize_loc = 0xff, position_loc = 0xff, layer_loc = 0xff;
if (layer_regid != regid(63, 0)) {
ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
}
- if (last_shader->shader->stream_output.num_outputs)
- tu6_setup_streamout(last_shader, &linkage, tf);
+ tu6_setup_streamout(cs, last_shader, &linkage);
+
+ /* The GPU hangs on some models when there are no outputs (xs_pack::CNT),
+ * at least when a DS is the last stage, so add a dummy output to keep it
+ * happy if there aren't any. We do this late in order to avoid emitting
+ * any unused code and make sure that optimizations don't remove it.
+ */
+ if (linkage.cnt == 0)
+ ir3_link_add(&linkage, 0, 0x1, linkage.max_loc);
/* map outputs of the last shader to VPC */
assert(linkage.cnt <= 32);
A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
}
- if (gs)
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count);
- else
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count);
+ tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
tu_cs_emit_array(cs, sp_out, sp_out_count);
- if (gs)
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count);
- else
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count);
+ tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vpc_dst_reg, sp_vpc_dst_count);
tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMID_CNTL, 1);
- tu_cs_emit(cs, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
+ tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
+ tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
+ A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
+ A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
+
+ tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
+ tu_cs_emit(cs, 0xffff00);
+
+ tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
+ tu_cs_emit(cs, 0);
+
+ tu_cs_emit_pkt4(cs, cfg->reg_pc_xs_out_cntl, 1);
+ tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
+ CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
+ CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
+ CONDREG(primitive_regid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
+
+ tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
+ tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
+ A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
+
+ tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
+ tu_cs_emit(cs, A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(layer_loc) | 0xff00);
+
+ tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
+ tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER));
+
+ tu_cs_emit_regs(cs, A6XX_PC_PRIMID_PASSTHRU(primid_passthru));
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs ? fs->total_in : 0) |
COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
- A6XX_VPC_CNTL_0_UNKLOC(0xff));
+ A6XX_VPC_CNTL_0_VIEWIDLOC(0xff));
+
+ if (hs) {
+ shader_info *hs_info = &hs->shader->nir->info;
+ uint32_t unknown_a831 = vs->output_size;
+
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
+ tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
+
+ /* Total attribute slots in HS incoming patch. */
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_INPUT_SIZE, 1);
+ tu_cs_emit(cs, patch_control_points * vs->output_size / 4);
+
+ /* for A650 this value seems to be local memory size per wave */
+ if (vshs_workgroup) {
+ const uint32_t wavesize = 64;
+ /* note: if HS is really just the VS extended, then this
+ * should be by MAX2(patch_control_points, hs_info->tess.tcs_vertices_out)
+ * however that doesn't match the blob, and fails some dEQP tests.
+ */
+ uint32_t prims_per_wave = wavesize / hs_info->tess.tcs_vertices_out;
+ uint32_t total_size = vs->output_size * patch_control_points * prims_per_wave;
+ unknown_a831 = DIV_ROUND_UP(total_size, wavesize);
+ }
+
+ tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
+ tu_cs_emit(cs, unknown_a831);
+
+ /* In SPIR-V generated from GLSL, the tessellation primitive params are
+ * are specified in the tess eval shader, but in SPIR-V generated from
+ * HLSL, they are specified in the tess control shader. */
+ shader_info *tess_info =
+ ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ?
+ &hs->shader->nir->info : &ds->shader->nir->info;
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1);
+ uint32_t output;
+ if (tess_info->tess.point_mode)
+ output = TESS_POINTS;
+ else if (tess_info->tess.primitive_mode == GL_ISOLINES)
+ output = TESS_LINES;
+ else if (tess_info->tess.ccw)
+ output = TESS_CCW_TRIS;
+ else
+ output = TESS_CW_TRIS;
+
+ enum a6xx_tess_spacing spacing;
+ switch (tess_info->tess.spacing) {
+ case TESS_SPACING_EQUAL:
+ spacing = TESS_EQUAL;
+ break;
+ case TESS_SPACING_FRACTIONAL_ODD:
+ spacing = TESS_FRACTIONAL_ODD;
+ break;
+ case TESS_SPACING_FRACTIONAL_EVEN:
+ spacing = TESS_FRACTIONAL_EVEN;
+ break;
+ case TESS_SPACING_UNSPECIFIED:
+ default:
+ unreachable("invalid tess spacing");
+ }
+ tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) |
+ A6XX_PC_TESS_CNTL_OUTPUT(output));
+
+ tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER);
+ tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER);
+ }
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
- tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
- A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
- A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
if (gs) {
uint32_t vertices_out, invocations, output, vec4_size;
/* this detects the tu_clear_blit path, which doesn't set ->nir */
if (gs->shader->nir) {
- tu6_emit_link_map(cs, vs, gs);
+ if (hs) {
+ tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER);
+ } else {
+ tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER);
+ }
vertices_out = gs->shader->nir->info.gs.vertices_out - 1;
output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive);
invocations = gs->shader->nir->info.gs.invocations - 1;
/* Size of per-primitive alloction in ldlw memory in vec4s. */
vec4_size = gs->shader->nir->info.gs.vertices_in *
- DIV_ROUND_UP(vs->shader->output_size, 4);
+ DIV_ROUND_UP(vs->output_size, 4);
} else {
vertices_out = 3;
output = TESS_CW_TRIS;
vec4_size = 0;
}
- uint32_t primitive_regid =
- ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_GS, 1);
- tu_cs_emit(cs, A6XX_VPC_PACK_GS_POSITIONLOC(position_loc) |
- A6XX_VPC_PACK_GS_PSIZELOC(pointsize_loc) |
- A6XX_VPC_PACK_GS_STRIDE_IN_VPC(linkage.max_loc));
-
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9105, 1);
- tu_cs_emit(cs, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
-
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809C, 1);
- tu_cs_emit(cs, CONDREG(layer_regid,
- A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
-
- uint32_t flags_regid = ir3_find_output_regid(gs,
- VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
-
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
- tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(linkage.cnt) |
- A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
-
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
- tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(linkage.max_loc) |
- CONDREG(pointsize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
- CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
- CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
-
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
tu_cs_emit(cs,
A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
tu_cs_emit(cs, 0);
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8003, 1);
- tu_cs_emit(cs, 0);
-
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9100, 1);
tu_cs_emit(cs, 0xff);
- tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9102, 1);
- tu_cs_emit(cs, 0xffff00);
-
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9B07, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_PC_MULTIVIEW_CNTL, 1);
tu_cs_emit(cs, 0);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
- tu_cs_emit(cs, vs->shader->output_size);
+ tu_cs_emit(cs, vs->output_size);
}
-
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
- tu_cs_emit(cs, A6XX_SP_PRIMITIVE_CNTL_VSOUT(linkage.cnt));
-
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
- tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(linkage.max_loc) |
- (last_shader->writes_psize ? A6XX_PC_PRIMITIVE_CNTL_1_PSIZE : 0));
}
static int
tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
{
uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
- uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
+ uint32_t ij_regid[IJ_COUNT];
uint32_t smask_in_regid;
- bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
+ bool sample_shading = fs->per_samp | fs->key.sample_shading;
bool enable_varyings = fs->total_in > 0;
samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
- ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
- ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
- ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
- ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
+ for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
+ ij_regid[i] = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
+
+ if (VALIDREG(ij_regid[IJ_LINEAR_SAMPLE]))
+ tu_finishme("linear sample varying");
+
+ if (VALIDREG(ij_regid[IJ_LINEAR_CENTROID]))
+ tu_finishme("linear centroid varying");
if (fs->num_sampler_prefetch > 0) {
- assert(VALIDREG(ij_pix_regid));
+ assert(VALIDREG(ij_regid[IJ_PERSP_PIXEL]));
/* also, it seems like ij_pix is *required* to be r0.x */
- assert(ij_pix_regid == regid(0, 0));
+ assert(ij_regid[IJ_PERSP_PIXEL] == regid(0, 0));
}
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
- A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
- tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
- A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
- 0xfc00fc00);
+ A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid[IJ_PERSP_SIZE]));
+ tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid[IJ_PERSP_CENTROID]) |
+ A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(ij_regid[IJ_LINEAR_CENTROID]));
tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
- A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
- 0x0000fc00);
+ A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid[IJ_PERSP_SAMPLE]) |
+ A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid[IJ_LINEAR_SAMPLE]));
tu_cs_emit(cs, 0xfc);
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
tu_cs_emit(cs, enable_varyings ? 3 : 1);
+ bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
+ bool need_size_persamp = false;
+ if (VALIDREG(ij_regid[IJ_PERSP_SIZE])) {
+ if (sample_shading)
+ need_size_persamp = true;
+ else
+ need_size = true;
+ }
+ if (VALIDREG(ij_regid[IJ_LINEAR_PIXEL]))
+ need_size = true;
+
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
tu_cs_emit(cs,
- CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
- CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
- CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
- COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
- COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
- COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
- A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
- COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
+ CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
+ CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
+ CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
+ COND(need_size, A6XX_GRAS_CNTL_SIZE) |
+ COND(need_size_persamp, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
+ COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
tu_cs_emit(cs,
- CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
- CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
- CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
+ CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
+ CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
+ CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
+ COND(need_size, A6XX_RB_RENDER_CONTROL0_SIZE) |
COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
- COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
- COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
- COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
- A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
- COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
+ COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
+ COND(fs->fragcoord_compmask != 0,
+ A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
tu_cs_emit(cs,
+ /* these two bits (UNK4/UNK5) relate to fragcoord
+ * without them, fragcoord is the same for all samples
+ */
+ COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK4) |
+ COND(sample_shading, A6XX_RB_RENDER_CONTROL1_UNK5) |
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
- CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
+ CONDREG(ij_regid[IJ_PERSP_SIZE], A6XX_RB_RENDER_CONTROL1_SIZE) |
COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
tu6_emit_fs_outputs(struct tu_cs *cs,
const struct ir3_shader_variant *fs,
uint32_t mrt_count, bool dual_src_blend,
- uint32_t render_components)
+ uint32_t render_components,
+ bool is_s8_uint)
{
- uint32_t smask_regid, posz_regid;
+ uint32_t smask_regid, posz_regid, stencilref_regid;
posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
+ stencilref_regid = ir3_find_output_regid(fs, FRAG_RESULT_STENCIL);
uint32_t fragdata_regid[8];
if (fs->color0_mrt) {
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
- COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE) |
- 0xfc000000);
+ A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
+ COND(dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
+ COND(fs->writes_stencilref, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
COND(dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
tu_cs_emit(cs, A6XX_RB_FS_OUTPUT_CNTL1_MRT(mrt_count));
enum a6xx_ztest_mode zmode;
- if (fs->no_earlyz || fs->has_kill || fs->writes_pos) {
+ if (fs->no_earlyz || fs->has_kill || fs->writes_pos || fs->writes_stencilref || is_s8_uint) {
zmode = A6XX_LATE_Z;
} else {
zmode = A6XX_EARLY_Z;
}
static void
-tu6_emit_geometry_consts(struct tu_cs *cs,
- const struct ir3_shader_variant *vs,
- const struct ir3_shader_variant *gs) {
- unsigned num_vertices = gs->shader->nir->info.gs.vertices_in;
-
- uint32_t params[4] = {
- vs->shader->output_size * num_vertices * 4, /* primitive stride */
- vs->shader->output_size * 4, /* vertex stride */
+tu6_emit_geom_tess_consts(struct tu_cs *cs,
+ const struct ir3_shader_variant *vs,
+ const struct ir3_shader_variant *hs,
+ const struct ir3_shader_variant *ds,
+ const struct ir3_shader_variant *gs,
+ uint32_t cps_per_patch)
+{
+ uint32_t num_vertices =
+ hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in;
+
+ uint32_t vs_params[4] = {
+ vs->output_size * num_vertices * 4, /* vs primitive stride */
+ vs->output_size * 4, /* vs vertex stride */
0,
0,
};
- uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
+ uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
- ARRAY_SIZE(params), params);
+ ARRAY_SIZE(vs_params), vs_params);
+
+ if (hs) {
+ assert(ds->type != MESA_SHADER_NONE);
+ uint32_t hs_params[4] = {
+ vs->output_size * num_vertices * 4, /* hs primitive stride */
+ vs->output_size * 4, /* hs vertex stride */
+ hs->output_size,
+ cps_per_patch,
+ };
+
+ uint32_t hs_base = hs->const_state->offsets.primitive_param;
+ tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0,
+ ARRAY_SIZE(hs_params), hs_params);
+ if (gs)
+ num_vertices = gs->shader->nir->info.gs.vertices_in;
+
+ uint32_t ds_params[4] = {
+ ds->output_size * num_vertices * 4, /* ds primitive stride */
+ ds->output_size * 4, /* ds vertex stride */
+ hs->output_size, /* hs vertex stride (dwords) */
+ hs->shader->nir->info.tess.tcs_vertices_out
+ };
+
+ uint32_t ds_base = ds->const_state->offsets.primitive_param;
+ tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0,
+ ARRAY_SIZE(ds_params), ds_params);
+ }
- uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
- tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
- ARRAY_SIZE(params), params);
+ if (gs) {
+ const struct ir3_shader_variant *prev = ds ? ds : vs;
+ uint32_t gs_params[4] = {
+ prev->output_size * num_vertices * 4, /* gs primitive stride */
+ prev->output_size * 4, /* gs vertex stride */
+ 0,
+ 0,
+ };
+ uint32_t gs_base = gs->const_state->offsets.primitive_param;
+ tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
+ ARRAY_SIZE(gs_params), gs_params);
+ }
}
static void
tu6_emit_program(struct tu_cs *cs,
struct tu_pipeline_builder *builder,
- const struct tu_bo *binary_bo,
- bool binning_pass,
- struct tu_streamout_state *tf)
+ bool binning_pass)
{
const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX];
const struct ir3_shader_variant *bs = builder->binning_variant;
+ const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
+ const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
gl_shader_stage stage = MESA_SHADER_VERTEX;
+ uint32_t cps_per_patch = builder->create_info->pTessellationState ?
+ builder->create_info->pTessellationState->patchControlPoints : 0;
STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
- tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
- tu_cs_emit(cs, 0xff); /* XXX */
+ tu_cs_emit_regs(cs, A6XX_HLSQ_INVALIDATE_CMD(
+ .vs_state = true,
+ .hs_state = true,
+ .ds_state = true,
+ .gs_state = true,
+ .fs_state = true,
+ .gfx_ibo = true));
/* Don't use the binning pass variant when GS is present because we don't
* support compiling correct binning pass variants with GS.
*/
if (binning_pass && !gs) {
vs = bs;
- tu6_emit_xs_config(cs, stage, bs,
- binary_bo->iova + builder->binning_vs_offset);
+ tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova);
stage++;
}
if (stage == MESA_SHADER_FRAGMENT && binning_pass)
fs = xs = NULL;
- tu6_emit_xs_config(cs, stage, xs,
- binary_bo->iova + builder->shader_offsets[stage]);
+ tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]);
}
tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
tu_cs_emit(cs, 0);
- tu6_emit_vpc(cs, vs, gs, fs, tf);
+ tu6_emit_vpc(cs, vs, hs, ds, gs, fs, cps_per_patch,
+ builder->device->physical_device->gpu_id == 650);
tu6_emit_vpc_varying_modes(cs, fs);
if (fs) {
tu6_emit_fs_inputs(cs, fs);
tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count,
builder->use_dual_src_blend,
- builder->render_components);
+ builder->render_components,
+ builder->depth_attachment_format == VK_FORMAT_S8_UINT);
} else {
/* TODO: check if these can be skipped if fs is disabled */
struct ir3_shader_variant dummy_variant = {};
tu6_emit_fs_inputs(cs, &dummy_variant);
tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count,
builder->use_dual_src_blend,
- builder->render_components);
+ builder->render_components,
+ builder->depth_attachment_format == VK_FORMAT_S8_UINT);
}
- if (gs)
- tu6_emit_geometry_consts(cs, vs, gs);
+ if (gs || hs) {
+ tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
+ }
}
static void
{
uint32_t vfd_decode_idx = 0;
uint32_t binding_instanced = 0; /* bitmask of instanced bindings */
+ uint32_t step_rate[MAX_VBS];
for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) {
const VkVertexInputBindingDescription *binding =
binding_instanced |= 1 << binding->binding;
*bindings_used |= 1 << binding->binding;
+ step_rate[binding->binding] = 1;
+ }
+
+ const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state =
+ vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
+ if (div_state) {
+ for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) {
+ const VkVertexInputBindingDivisorDescriptionEXT *desc =
+ &div_state->pVertexBindingDivisors[i];
+ step_rate[desc->binding] = desc->divisor;
+ }
}
/* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */
&info->pVertexAttributeDescriptions[i];
uint32_t input_idx;
+ assert(*bindings_used & BIT(attr->binding));
+
for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) {
if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location)
break;
.swap = format.swap,
.unk30 = 1,
._float = !vk_format_is_int(attr->format)),
- A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1));
+ A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding]));
tu_cs_emit_regs(cs,
A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx,
.decode_cnt = vfd_decode_idx));
}
-static uint32_t
-tu6_guardband_adj(uint32_t v)
-{
- if (v > 256)
- return (uint32_t)(511.0 - 65.0 * (log2(v) - 8.0));
- else
- return 511;
-}
-
void
tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport)
{
assert(min.y >= 0 && min.y < max.y);
VkExtent2D guardband_adj;
- guardband_adj.width = tu6_guardband_adj(max.x - min.x);
- guardband_adj.height = tu6_guardband_adj(max.y - min.y);
-
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET_0, 6);
- tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XOFFSET_0(offsets[0]).value);
- tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_XSCALE_0(scales[0]).value);
- tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YOFFSET_0(offsets[1]).value);
- tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_YSCALE_0(scales[1]).value);
- tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZOFFSET_0(offsets[2]).value);
- tu_cs_emit(cs, A6XX_GRAS_CL_VPORT_ZSCALE_0(scales[2]).value);
-
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
- tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(min.x) |
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(min.y));
- tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(max.x - 1) |
- A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(max.y - 1));
+ guardband_adj.width = fd_calc_guardband(offsets[0], scales[0], false);
+ guardband_adj.height = fd_calc_guardband(offsets[1], scales[1], false);
+
+ tu_cs_emit_regs(cs,
+ A6XX_GRAS_CL_VPORT_XOFFSET(0, offsets[0]),
+ A6XX_GRAS_CL_VPORT_XSCALE(0, scales[0]),
+ A6XX_GRAS_CL_VPORT_YOFFSET(0, offsets[1]),
+ A6XX_GRAS_CL_VPORT_YSCALE(0, scales[1]),
+ A6XX_GRAS_CL_VPORT_ZOFFSET(0, offsets[2]),
+ A6XX_GRAS_CL_VPORT_ZSCALE(0, scales[2]));
+
+ tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0), 2);
+ tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(min.x) |
+ A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(min.y));
+ tu_cs_emit(cs, A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(max.x - 1) |
+ A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(max.y - 1));
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1);
tu_cs_emit(cs,
float z_clamp_max = MAX2(viewport->minDepth, viewport->maxDepth);
tu_cs_emit_regs(cs,
- A6XX_GRAS_CL_Z_CLAMP_MIN(z_clamp_min),
- A6XX_GRAS_CL_Z_CLAMP_MAX(z_clamp_max));
+ A6XX_GRAS_CL_Z_CLAMP_MIN(0, z_clamp_min),
+ A6XX_GRAS_CL_Z_CLAMP_MAX(0, z_clamp_max));
tu_cs_emit_regs(cs,
A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
void
tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor)
{
- const VkOffset2D min = scissor->offset;
- const VkOffset2D max = {
+ VkOffset2D min = scissor->offset;
+ VkOffset2D max = {
scissor->offset.x + scissor->extent.width,
scissor->offset.y + scissor->extent.height,
};
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
- tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) |
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y));
- tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) |
- A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1));
+ /* special case for empty scissor with max == 0 to avoid overflow */
+ if (max.x == 0)
+ min.x = max.x = 1;
+ if (max.y == 0)
+ min.y = max.y = 1;
+
+ /* avoid overflow with large scissor
+ * note the max will be limited to min - 1, so that empty scissor works
+ */
+ uint32_t scissor_max = BITFIELD_MASK(15);
+ min.x = MIN2(scissor_max, min.x);
+ min.y = MIN2(scissor_max, min.y);
+ max.x = MIN2(scissor_max, max.x);
+ max.y = MIN2(scissor_max, max.y);
+
+ tu_cs_emit_regs(cs,
+ A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0, .x = min.x, .y = min.y),
+ A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0, .x = max.x - 1, .y = max.y - 1));
}
void
const VkPipelineDepthStencilStateCreateInfo *ds_info,
const VkPipelineRasterizationStateCreateInfo *rast_info)
{
- assert(!ds_info->depthBoundsTestEnable);
-
uint32_t rb_depth_cntl = 0;
if (ds_info->depthTestEnable) {
rb_depth_cntl |=
A6XX_RB_DEPTH_CNTL_Z_ENABLE |
A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
- A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+ A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */
if (rast_info->depthClampEnable)
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE;
rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
}
+ if (ds_info->depthBoundsTestEnable)
+ rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
+
tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1);
tu_cs_emit(cs, rb_depth_cntl);
}
}
static VkResult
-tu_pipeline_create(struct tu_device *dev,
- struct tu_pipeline_layout *layout,
- bool compute,
- const VkAllocationCallbacks *pAllocator,
- struct tu_pipeline **out_pipeline)
-{
- struct tu_pipeline *pipeline =
- vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8,
- VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
- if (!pipeline)
- return VK_ERROR_OUT_OF_HOST_MEMORY;
+tu_pipeline_allocate_cs(struct tu_device *dev,
+ struct tu_pipeline *pipeline,
+ struct tu_pipeline_builder *builder,
+ struct ir3_shader_variant *compute)
+{
+ uint32_t size = 2048 + tu6_load_state_size(pipeline, compute);
+
+ /* graphics case: */
+ if (builder) {
+ for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
+ if (builder->variants[i])
+ size += builder->variants[i]->info.sizedwords;
+ }
- tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048);
+ size += builder->binning_variant->info.sizedwords;
+ } else {
+ size += compute->info.sizedwords;
+ }
+
+ tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size);
/* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note
* that LOAD_STATE can potentially take up a large amount of space so we
* calculate its size explicitly.
*/
- unsigned load_state_size = tu6_load_state_size(layout, compute);
- VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size);
- if (result != VK_SUCCESS) {
- vk_free2(&dev->alloc, pAllocator, pipeline);
- return result;
- }
-
- *out_pipeline = pipeline;
-
- return VK_SUCCESS;
+ return tu_cs_reserve_space(&pipeline->cs, size);
}
static void
tu_pipeline_shader_key_init(struct ir3_shader_key *key,
const VkGraphicsPipelineCreateInfo *pipeline_info)
{
- bool has_gs = false;
- bool msaa = false;
- if (pipeline_info) {
- for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
- if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
- has_gs = true;
- break;
- }
+ for (uint32_t i = 0; i < pipeline_info->stageCount; i++) {
+ if (pipeline_info->pStages[i].stage == VK_SHADER_STAGE_GEOMETRY_BIT) {
+ key->has_gs = true;
+ break;
}
+ }
- const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
- const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
- vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
- if (!pipeline_info->pRasterizationState->rasterizerDiscardEnable &&
- (msaa_info->rasterizationSamples > 1 ||
- /* also set msaa key when sample location is not the default
- * since this affects varying interpolation */
- (sample_locations && sample_locations->sampleLocationsEnable))) {
- msaa = true;
- }
+ if (pipeline_info->pRasterizationState->rasterizerDiscardEnable)
+ return;
+
+ const VkPipelineMultisampleStateCreateInfo *msaa_info = pipeline_info->pMultisampleState;
+ const struct VkPipelineSampleLocationsStateCreateInfoEXT *sample_locations =
+ vk_find_struct_const(msaa_info->pNext, PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
+ if (msaa_info->rasterizationSamples > 1 ||
+ /* also set msaa key when sample location is not the default
+ * since this affects varying interpolation */
+ (sample_locations && sample_locations->sampleLocationsEnable)) {
+ key->msaa = true;
}
- /* TODO: Populate the remaining fields of ir3_shader_key. */
- *key = (struct ir3_shader_key) {
- .has_gs = has_gs,
- .msaa = msaa,
- };
+ /* note: not actually used by ir3, just checked in tu6_emit_fs_inputs */
+ if (msaa_info->sampleShadingEnable)
+ key->sample_shading = true;
+
+ /* We set this after we compile to NIR because we need the prim mode */
+ key->tessellation = IR3_TESS_NONE;
+}
+
+static uint32_t
+tu6_get_tessmode(struct tu_shader* shader)
+{
+ uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode;
+ switch (primitive_mode) {
+ case GL_ISOLINES:
+ return IR3_TESS_ISOLINES;
+ case GL_TRIANGLES:
+ return IR3_TESS_TRIANGLES;
+ case GL_QUADS:
+ return IR3_TESS_QUADS;
+ case GL_NONE:
+ return IR3_TESS_NONE;
+ default:
+ unreachable("bad tessmode");
+ }
+}
+
+static uint64_t
+tu_upload_variant(struct tu_pipeline *pipeline,
+ const struct ir3_shader_variant *variant)
+{
+ struct tu_cs_memory memory;
+
+ if (!variant)
+ return 0;
+
+ /* this expects to get enough alignment because shaders are allocated first
+ * and sizedwords is always aligned correctly
+ * note: an assert in tu6_emit_xs_config validates the alignment
+ */
+ tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory);
+
+ memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords);
+ return memory.iova;
}
static VkResult
-tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder)
+tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder,
+ struct tu_pipeline *pipeline)
{
+ const struct ir3_compiler *compiler = builder->device->compiler;
const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = {
NULL
};
stage_infos[stage] = &builder->create_info->pStages[i];
}
- struct ir3_shader_key key;
+ struct ir3_shader_key key = {};
tu_pipeline_shader_key_init(&key, builder->create_info);
for (gl_shader_stage stage = MESA_SHADER_VERTEX;
if (!shader)
return VK_ERROR_OUT_OF_HOST_MEMORY;
+ /* In SPIR-V generated from GLSL, the primitive mode is specified in the
+ * tessellation evaluation shader, but in SPIR-V generated from HLSL,
+ * the mode is specified in the tessellation control shader. */
+ if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) &&
+ key.tessellation == IR3_TESS_NONE) {
+ key.tessellation = tu6_get_tessmode(shader);
+ }
+
builder->shaders[stage] = shader;
}
- for (gl_shader_stage stage = MESA_SHADER_STAGES - 1;
- stage > MESA_SHADER_NONE; stage--) {
+ struct tu_shader *gs = builder->shaders[MESA_SHADER_GEOMETRY];
+ key.layer_zero =
+ !gs || !(gs->ir3_shader->nir->info.outputs_written & VARYING_SLOT_LAYER);
+
+ pipeline->tess.patch_type = key.tessellation;
+
+ for (gl_shader_stage stage = MESA_SHADER_VERTEX;
+ stage < MESA_SHADER_STAGES; stage++) {
if (!builder->shaders[stage])
continue;
&key, false, &created);
if (!builder->variants[stage])
return VK_ERROR_OUT_OF_HOST_MEMORY;
+ }
+
+ uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler);
+
+ key.safe_constlen = true;
+
+ for (gl_shader_stage stage = MESA_SHADER_VERTEX;
+ stage < MESA_SHADER_STAGES; stage++) {
+ if (!builder->shaders[stage])
+ continue;
- builder->shader_offsets[stage] = builder->shader_total_size;
- builder->shader_total_size +=
- sizeof(uint32_t) * builder->variants[stage]->info.sizedwords;
+ if (safe_constlens & (1 << stage)) {
+ bool created;
+ builder->variants[stage] =
+ ir3_shader_get_variant(builder->shaders[stage]->ir3_shader,
+ &key, false, &created);
+ if (!builder->variants[stage])
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
+ }
}
const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX];
struct ir3_shader_variant *variant;
- if (vs->ir3_shader->stream_output.num_outputs) {
+ if (vs->ir3_shader->stream_output.num_outputs ||
+ !ir3_has_binning_vs(&key)) {
variant = builder->variants[MESA_SHADER_VERTEX];
} else {
bool created;
+ key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX));
variant = ir3_shader_get_variant(vs->ir3_shader, &key,
true, &created);
if (!variant)
return VK_ERROR_OUT_OF_HOST_MEMORY;
}
- builder->binning_vs_offset = builder->shader_total_size;
- builder->shader_total_size +=
- sizeof(uint32_t) * variant->info.sizedwords;
builder->binning_variant = variant;
return VK_SUCCESS;
}
-static VkResult
-tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder,
- struct tu_pipeline *pipeline)
-{
- struct tu_bo *bo = &pipeline->program.binary_bo;
-
- VkResult result =
- tu_bo_init_new(builder->device, bo, builder->shader_total_size);
- if (result != VK_SUCCESS)
- return result;
-
- result = tu_bo_map(builder->device, bo);
- if (result != VK_SUCCESS)
- return result;
-
- for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
- const struct ir3_shader_variant *variant = builder->variants[i];
- if (!variant)
- continue;
-
- memcpy(bo->map + builder->shader_offsets[i], variant->bin,
- sizeof(uint32_t) * variant->info.sizedwords);
- }
-
- if (builder->binning_variant) {
- const struct ir3_shader_variant *variant = builder->binning_variant;
- memcpy(bo->map + builder->binning_vs_offset, variant->bin,
- sizeof(uint32_t) * variant->info.sizedwords);
- }
-
- return VK_SUCCESS;
-}
-
static void
tu_pipeline_builder_parse_dynamic(struct tu_pipeline_builder *builder,
struct tu_pipeline *pipeline)
struct tu_shader *shader,
struct ir3_shader_variant *v)
{
- link->ubo_state = v->shader->ubo_state;
- link->const_state = v->shader->const_state;
+ link->const_state = *ir3_const_state(v);
link->constlen = v->constlen;
link->push_consts = shader->push_consts;
}
{
struct tu_cs prog_cs;
tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
- tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout);
- pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
+ tu6_emit_program(&prog_cs, builder, false);
+ pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
- tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout);
- pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
+ tu6_emit_program(&prog_cs, builder, true);
+ pipeline->program.binning_state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
VkShaderStageFlags stages = 0;
for (unsigned i = 0; i < builder->create_info->stageCount; i++) {
MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
tu6_emit_vertex_input(&vi_cs, vs, vi_info,
&pipeline->vi.bindings_used);
- pipeline->vi.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
+ pipeline->vi.state = tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
if (bs) {
tu_cs_begin_sub_stream(&pipeline->cs,
MAX_VERTEX_ATTRIBS * 7 + 2, &vi_cs);
tu6_emit_vertex_input(
&vi_cs, bs, vi_info, &pipeline->vi.bindings_used);
- pipeline->vi.binning_state_ib =
- tu_cs_end_sub_stream(&pipeline->cs, &vi_cs);
+ pipeline->vi.binning_state =
+ tu_cs_end_draw_state(&pipeline->cs, &vi_cs);
}
}
tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs,
uint32_t id, uint32_t size)
{
- struct ts_cs_memory memory;
+ assert(id < ARRAY_SIZE(pipeline->dynamic_state));
if (pipeline->dynamic_state_mask & BIT(id))
return false;
- /* TODO: share this logc with tu_cmd_dynamic_state */
- tu_cs_alloc(&pipeline->cs, size, 1, &memory);
- tu_cs_init_external(cs, memory.map, memory.map + size);
- tu_cs_begin(cs);
- tu_cs_reserve_space(cs, size);
-
- assert(id < ARRAY_SIZE(pipeline->dynamic_state));
- pipeline->dynamic_state[id].iova = memory.iova;
- pipeline->dynamic_state[id].size = size;
+ pipeline->dynamic_state[id] = tu_cs_draw_state(&pipeline->cs, cs, size);
return true;
}
+static void
+tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder,
+ struct tu_pipeline *pipeline)
+{
+ const VkPipelineTessellationStateCreateInfo *tess_info =
+ builder->create_info->pTessellationState;
+
+ if (!tess_info)
+ return;
+
+ assert(pipeline->ia.primtype == DI_PT_PATCHES0);
+ assert(tess_info->patchControlPoints <= 32);
+ pipeline->ia.primtype += tess_info->patchControlPoints;
+ const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info =
+ vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
+ pipeline->tess.upper_left_domain_origin = !domain_info ||
+ domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
+ const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL];
+ const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL];
+ pipeline->tess.param_stride = hs->output_size * 4;
+ pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1;
+ pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1;
+}
+
static void
tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder,
struct tu_pipeline *pipeline)
const VkPipelineRasterizationStateCreateInfo *rast_info =
builder->create_info->pRasterizationState;
- assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL);
+ enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode);
+
+ bool depth_clip_disable = rast_info->depthClampEnable;
+
+ const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
+ vk_find_struct_const(rast_info, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
+ if (depth_clip_state)
+ depth_clip_disable = !depth_clip_state->depthClipEnable;
struct tu_cs cs;
- tu_cs_begin_sub_stream(&pipeline->cs, 7, &cs);
+ pipeline->rast_state = tu_cs_draw_state(&pipeline->cs, &cs, 9);
tu_cs_emit_regs(&cs,
A6XX_GRAS_CL_CNTL(
- .znear_clip_disable = rast_info->depthClampEnable,
- .zfar_clip_disable = rast_info->depthClampEnable,
+ .znear_clip_disable = depth_clip_disable,
+ .zfar_clip_disable = depth_clip_disable,
+ /* TODO should this be depth_clip_disable instead? */
.unk5 = rast_info->depthClampEnable,
.zero_gb_scale_z = 1,
.vp_clip_code_ignore = 1));
+
+ tu_cs_emit_regs(&cs,
+ A6XX_VPC_POLYGON_MODE(mode));
+
+ tu_cs_emit_regs(&cs,
+ A6XX_PC_POLYGON_MODE(mode));
+
/* move to hw ctx init? */
- tu_cs_emit_regs(&cs, A6XX_GRAS_UNKNOWN_8001());
tu_cs_emit_regs(&cs,
A6XX_GRAS_SU_POINT_MINMAX(.min = 1.0f / 16.0f, .max = 4092.0f),
A6XX_GRAS_SU_POINT_SIZE(1.0f));
- pipeline->rast.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
-
pipeline->gras_su_cntl =
tu6_gras_su_cntl(rast_info, builder->samples);
? ds_info : &dummy_ds_info;
struct tu_cs cs;
- tu_cs_begin_sub_stream(&pipeline->cs, 6, &cs);
+ pipeline->ds_state = tu_cs_draw_state(&pipeline->cs, &cs, 6);
/* move to hw ctx init? */
tu_cs_emit_regs(&cs, A6XX_RB_ALPHA_CONTROL());
builder->create_info->pRasterizationState);
tu6_emit_stencil_control(&cs, ds_info);
- pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
+ if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) {
+ tu_cs_emit_regs(&cs,
+ A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds),
+ A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds));
+ }
if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) {
tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff,
: &dummy_blend_info;
struct tu_cs cs;
- tu_cs_begin_sub_stream(&pipeline->cs, MAX_RTS * 3 + 4, &cs);
+ pipeline->blend_state =
+ tu_cs_draw_state(&pipeline->cs, &cs, blend_info->attachmentCount * 3 + 4);
uint32_t blend_enable_mask;
tu6_emit_rb_mrt_controls(&cs, blend_info,
tu6_emit_blend_control(&cs, blend_enable_mask,
builder->use_dual_src_blend, msaa_info);
- pipeline->blend.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs);
+ assert(cs.cur == cs.end); /* validate draw state size */
if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_BLEND_CONSTANTS, 5)) {
tu_cs_emit_pkt4(&cs, REG_A6XX_RB_BLEND_RED_F32, 4);
const VkAllocationCallbacks *alloc)
{
tu_cs_finish(&pipeline->cs);
-
- if (pipeline->program.binary_bo.gem_handle)
- tu_bo_finish(dev, &pipeline->program.binary_bo);
}
static VkResult
tu_pipeline_builder_build(struct tu_pipeline_builder *builder,
struct tu_pipeline **pipeline)
{
- VkResult result = tu_pipeline_create(builder->device, builder->layout,
- false, builder->alloc, pipeline);
- if (result != VK_SUCCESS)
- return result;
+ VkResult result;
+
+ *pipeline = vk_object_zalloc(&builder->device->vk, builder->alloc,
+ sizeof(**pipeline), VK_OBJECT_TYPE_PIPELINE);
+ if (!*pipeline)
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
(*pipeline)->layout = builder->layout;
/* compile and upload shaders */
- result = tu_pipeline_builder_compile_shaders(builder);
- if (result == VK_SUCCESS)
- result = tu_pipeline_builder_upload_shaders(builder, *pipeline);
+ result = tu_pipeline_builder_compile_shaders(builder, *pipeline);
if (result != VK_SUCCESS) {
- tu_pipeline_finish(*pipeline, builder->device, builder->alloc);
- vk_free2(&builder->device->alloc, builder->alloc, *pipeline);
- *pipeline = VK_NULL_HANDLE;
+ vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
+ return result;
+ }
+ result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL);
+ if (result != VK_SUCCESS) {
+ vk_object_free(&builder->device->vk, builder->alloc, *pipeline);
return result;
}
+ for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
+ builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]);
+
+ builder->binning_vs_iova =
+ tu_upload_variant(*pipeline, builder->binning_variant);
+
tu_pipeline_builder_parse_dynamic(builder, *pipeline);
tu_pipeline_builder_parse_shader_stages(builder, *pipeline);
tu_pipeline_builder_parse_vertex_input(builder, *pipeline);
tu_pipeline_builder_parse_input_assembly(builder, *pipeline);
+ tu_pipeline_builder_parse_tessellation(builder, *pipeline);
tu_pipeline_builder_parse_viewport(builder, *pipeline);
tu_pipeline_builder_parse_rasterization(builder, *pipeline);
tu_pipeline_builder_parse_depth_stencil(builder, *pipeline);
return final_result;
}
-static VkResult
-tu_compute_upload_shader(VkDevice device,
- struct tu_pipeline *pipeline,
- struct ir3_shader_variant *v)
-{
- TU_FROM_HANDLE(tu_device, dev, device);
- struct tu_bo *bo = &pipeline->program.binary_bo;
-
- uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords;
- VkResult result =
- tu_bo_init_new(dev, bo, shader_size);
- if (result != VK_SUCCESS)
- return result;
-
- result = tu_bo_map(dev, bo);
- if (result != VK_SUCCESS)
- return result;
-
- memcpy(bo->map, v->bin, shader_size);
-
- return VK_SUCCESS;
-}
-
-
static VkResult
tu_compute_pipeline_create(VkDevice device,
VkPipelineCache _cache,
*pPipeline = VK_NULL_HANDLE;
- result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline);
- if (result != VK_SUCCESS)
- return result;
+ pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
+ VK_OBJECT_TYPE_PIPELINE);
+ if (!pipeline)
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
pipeline->layout = layout;
- struct ir3_shader_key key;
- tu_pipeline_shader_key_init(&key, NULL);
+ struct ir3_shader_key key = {};
struct tu_shader *shader =
tu_shader_create(dev, MESA_SHADER_COMPUTE, stage_info, layout, pAllocator);
goto fail;
}
+ pipeline->active_desc_sets = shader->active_desc_sets;
+
bool created;
struct ir3_shader_variant *v =
ir3_shader_get_variant(shader->ir3_shader, &key, false, &created);
- if (!v)
+ if (!v) {
+ result = VK_ERROR_OUT_OF_HOST_MEMORY;
goto fail;
+ }
tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE],
shader, v);
- result = tu_compute_upload_shader(device, pipeline, v);
+ result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v);
if (result != VK_SUCCESS)
goto fail;
+ uint64_t shader_iova = tu_upload_variant(pipeline, v);
+
for (int i = 0; i < 3; i++)
pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i];
struct tu_cs prog_cs;
tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs);
- tu6_emit_cs_config(&prog_cs, shader, v, pipeline->program.binary_bo.iova);
- pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
+ tu6_emit_cs_config(&prog_cs, shader, v, shader_iova);
+ pipeline->program.state = tu_cs_end_draw_state(&pipeline->cs, &prog_cs);
tu6_emit_load_state(pipeline, true);
if (shader)
tu_shader_destroy(dev, shader, pAllocator);
- tu_pipeline_finish(pipeline, dev, pAllocator);
- vk_free2(&dev->alloc, pAllocator, pipeline);
+ vk_object_free(&dev->vk, pAllocator, pipeline);
return result;
}
return;
tu_pipeline_finish(pipeline, dev, pAllocator);
- vk_free2(&dev->alloc, pAllocator, pipeline);
+ vk_object_free(&dev->vk, pAllocator, pipeline);
}
projects / mesa.git / blobdiff