etnaviv: remove dead code
[mesa.git] / src / freedreno / vulkan / tu_pipeline.c
index 54239280daa4f4df18820ff8b6ea20c5d825b17b..aa22d1c2a1f69b18b3404bce1ddc133d76658666 100644 (file)
@@ -454,9 +454,6 @@ tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
    if (fs->instrlen)
       sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
 
-   tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A99E, 1);
-   tu_cs_emit(cs, 0);
-
    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
    tu_cs_emit(cs, 0);
 
@@ -701,6 +698,27 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
    ij_cent_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
    ij_size_regid   = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
 
+   if (fs->num_sampler_prefetch > 0) {
+      assert(VALIDREG(ij_pix_regid));
+      /* also, it seems like ij_pix is *required* to be r0.x */
+      assert(ij_pix_regid == regid(0, 0));
+   }
+
+   tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
+   tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
+         A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
+         0x7000);    // XXX);
+   for (int i = 0; i < fs->num_sampler_prefetch; i++) {
+      const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
+      tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
+                     A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
+                     A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
+                     A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
+                     A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
+                     COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
+                     A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
+   }
+
    tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
    tu_cs_emit(cs, 0x7);
    tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
@@ -904,6 +922,10 @@ static void
 tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
                     uint32_t opcode, enum a6xx_state_block block)
 {
+   /* dummy variant */
+   if (!v->shader)
+      return;
+
    const struct ir3_const_state *const_state = &v->shader->const_state;
    uint32_t base = const_state->offsets.immediate;
    int size = const_state->immediates_count;
@@ -920,7 +942,7 @@ tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
    tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
                   CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
                   CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
-                  CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_SHADER) |
+                  CP_LOAD_STATE6_0_STATE_BLOCK(block) |
                   CP_LOAD_STATE6_0_NUM_UNIT(size));
    tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
    tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
@@ -1137,7 +1159,7 @@ tu6_emit_gras_unknowns(struct tu_cs *cs)
    tu_cs_emit(cs, 0x80);
    tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
    tu_cs_emit(cs, 0x0);
-   tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8004, 1);
+   tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
    tu_cs_emit(cs, 0x0);
 }
 
@@ -1566,12 +1588,13 @@ tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder,
       struct ir3_shader *shader = builder->shaders[i]->variants[0].shader;
 
       link->ubo_state = shader->ubo_state;
+      link->const_state = shader->const_state;
       link->constlen = builder->shaders[i]->variants[0].constlen;
-      link->offset_ubo = shader->const_state.offsets.ubo;
-      link->num_ubo = shader->const_state.num_ubos;
       link->texture_map = builder->shaders[i]->texture_map;
       link->sampler_map = builder->shaders[i]->sampler_map;
       link->ubo_map = builder->shaders[i]->ubo_map;
+      link->ssbo_map = builder->shaders[i]->ssbo_map;
+      link->image_mapping =  builder->shaders[i]->variants[0].image_mapping;
    }
 }