case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
return DI_PT_TRILIST;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
- return DI_PT_TRILIST;
+ return DI_PT_TRISTRIP;
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
return DI_PT_TRIFAN;
case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack);
- if (vs->num_samp)
+ if (vs->need_pixlod)
sp_vs_ctrl |= A6XX_SP_VS_CTRL_REG0_PIXLODENABLE;
uint32_t sp_vs_config = A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
tu_cs_emit(cs, vs->instrlen);
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_VS_CNTL, 1);
- tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) | 0x100);
+ tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
+ A6XX_HLSQ_VS_CNTL_ENABLED);
}
static void
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack);
if (fs->total_in > 0 || fs->frag_coord)
sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_VARYING;
- if (fs->num_samp > 0)
+ if (fs->need_pixlod)
sp_fs_ctrl |= A6XX_SP_FS_CTRL_REG0_PIXLODENABLE;
uint32_t sp_fs_config = A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
if (fs->instrlen)
sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A99E, 1);
- tu_cs_emit(cs, 0x7fc0);
-
tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
tu_cs_emit(cs, 0);
tu_cs_emit(cs, fs->instrlen);
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL, 1);
- tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) | 0x100);
+ tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
+ A6XX_HLSQ_FS_CNTL_ENABLED);
}
static void
const struct ir3_shader_variant *vs)
{
const uint32_t vertexid_regid =
- ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
+ ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
const uint32_t instanceid_regid =
ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
ir3_find_output_regid(vs, VARYING_SLOT_POS);
const uint32_t pointsize_regid =
ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
- uint32_t pointsize_loc = 0xff;
- if (position_regid != regid(63, 0))
+ uint32_t pointsize_loc = 0xff, position_loc = 0xff;
+ if (position_regid != regid(63, 0)) {
+ position_loc = linkage.max_loc;
ir3_link_add(&linkage, position_regid, 0xf, linkage.max_loc);
+ }
if (pointsize_regid != regid(63, 0)) {
pointsize_loc = linkage.max_loc;
ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc);
0xff00ff00);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1);
- tu_cs_emit(cs, A6XX_VPC_PACK_NUMNONPOSVAR(fs->total_in) |
+ tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) |
A6XX_VPC_PACK_PSIZELOC(pointsize_loc) |
A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc));
tu_cs_emit_array(cs, ps_repl_modes, 8);
}
+#define VALIDREG(r) ((r) != regid(63,0))
+#define CONDREG(r, val) COND(VALIDREG(r), (val))
+
static void
-tu6_emit_fs_system_values(struct tu_cs *cs,
- const struct ir3_shader_variant *fs)
-{
- const uint32_t frontfacing_regid =
- ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
- const uint32_t sampleid_regid =
- ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
- const uint32_t samplemaskin_regid =
- ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
- const uint32_t fragcoord_xy_regid =
- ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
- const uint32_t fragcoord_zw_regid = (fragcoord_xy_regid != regid(63, 0))
- ? (fragcoord_xy_regid + 2)
- : fragcoord_xy_regid;
- const uint32_t varyingcoord_regid =
- ir3_find_sysval_regid(fs, SYSTEM_VALUE_VARYING_COORD);
+tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
+{
+ uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
+ uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
+ uint32_t smask_in_regid;
+
+ bool sample_shading = fs->per_samp; /* TODO | key->sample_shading; */
+ bool enable_varyings = fs->total_in > 0;
+
+ samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
+ smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
+ face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
+ coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
+ zwcoord_regid = VALIDREG(coord_regid) ? coord_regid + 2 : regid(63, 0);
+ ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
+ ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
+ ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
+ ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
+
+ if (fs->num_sampler_prefetch > 0) {
+ assert(VALIDREG(ij_pix_regid));
+ /* also, it seems like ij_pix is *required* to be r0.x */
+ assert(ij_pix_regid == regid(0, 0));
+ }
+
+ tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
+ tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
+ A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
+ 0x7000); // XXX);
+ for (int i = 0; i < fs->num_sampler_prefetch; i++) {
+ const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
+ tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
+ A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
+ A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
+ A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
+ A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
+ COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
+ A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
+ }
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
tu_cs_emit(cs, 0x7);
- tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(frontfacing_regid) |
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(sampleid_regid) |
- A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samplemaskin_regid) |
- 0xfc000000);
- tu_cs_emit(cs,
- A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(varyingcoord_regid) |
- 0xfcfcfc00);
- tu_cs_emit(cs,
- A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(fragcoord_xy_regid) |
- A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(fragcoord_zw_regid) |
- 0x0000fcfc);
+ tu_cs_emit(cs, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
+ A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
+ A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
+ A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
+ tu_cs_emit(cs, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
+ A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
+ 0xfc00fc00);
+ tu_cs_emit(cs, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
+ A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
+ A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
+ 0x0000fc00);
tu_cs_emit(cs, 0xfc);
-}
-static void
-tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
-{
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
- tu_cs_emit(cs, fs->total_in > 0 ? 3 : 1);
+ tu_cs_emit(cs, enable_varyings ? 3 : 1);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A982, 1);
tu_cs_emit(cs, 0); /* XXX */
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
tu_cs_emit(cs, 0xff); /* XXX */
- uint32_t gras_cntl = 0;
- if (fs->total_in > 0)
- gras_cntl |= A6XX_GRAS_CNTL_VARYING;
- if (fs->frag_coord) {
- gras_cntl |= A6XX_GRAS_CNTL_UNK3 | A6XX_GRAS_CNTL_XCOORD |
- A6XX_GRAS_CNTL_YCOORD | A6XX_GRAS_CNTL_ZCOORD |
- A6XX_GRAS_CNTL_WCOORD;
- }
-
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
- tu_cs_emit(cs, gras_cntl);
-
- uint32_t rb_render_control = 0;
- if (fs->total_in > 0) {
- rb_render_control =
- A6XX_RB_RENDER_CONTROL0_VARYING | A6XX_RB_RENDER_CONTROL0_UNK10;
- }
- if (fs->frag_coord) {
- rb_render_control |=
- A6XX_RB_RENDER_CONTROL0_UNK3 | A6XX_RB_RENDER_CONTROL0_XCOORD |
- A6XX_RB_RENDER_CONTROL0_YCOORD | A6XX_RB_RENDER_CONTROL0_ZCOORD |
- A6XX_RB_RENDER_CONTROL0_WCOORD;
- }
+ tu_cs_emit(cs,
+ CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
+ CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
+ CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
+ COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
+ COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
+ COND(fs->frag_coord,
+ A6XX_GRAS_CNTL_SIZE |
+ A6XX_GRAS_CNTL_XCOORD |
+ A6XX_GRAS_CNTL_YCOORD |
+ A6XX_GRAS_CNTL_ZCOORD |
+ A6XX_GRAS_CNTL_WCOORD) |
+ COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
- tu_cs_emit(cs, rb_render_control);
- tu_cs_emit(cs, (fs->frag_face ? A6XX_RB_RENDER_CONTROL1_FACENESS : 0));
+ tu_cs_emit(cs,
+ CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
+ CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
+ CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
+ COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
+ COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
+ COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
+ COND(fs->frag_coord,
+ A6XX_RB_RENDER_CONTROL0_SIZE |
+ A6XX_RB_RENDER_CONTROL0_XCOORD |
+ A6XX_RB_RENDER_CONTROL0_YCOORD |
+ A6XX_RB_RENDER_CONTROL0_ZCOORD |
+ A6XX_RB_RENDER_CONTROL0_WCOORD) |
+ COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
+ tu_cs_emit(cs,
+ CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
+ CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
+ CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
+ COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
}
static void
const struct ir3_shader_variant *fs,
uint32_t mrt_count)
{
- const uint32_t fragdepth_regid =
- ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
+ uint32_t smask_regid, posz_regid;
+
+ posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
+ smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
+
uint32_t fragdata_regid[8];
if (fs->color0_mrt) {
fragdata_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
}
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
- tu_cs_emit(
- cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(fragdepth_regid) | 0xfcfc0000);
+ tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
+ A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
+ 0xfc000000);
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
uint32_t gras_su_depth_plane_cntl = 0;
uint32_t rb_depth_plane_cntl = 0;
- if (fs->has_kill | fs->writes_pos) {
+ if (fs->no_earlyz | fs->writes_pos) {
gras_su_depth_plane_cntl |= A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
rb_depth_plane_cntl |= A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z;
}
}
}
+static void
+tu6_emit_immediates(struct tu_cs *cs, const struct ir3_shader_variant *v,
+ uint32_t opcode, enum a6xx_state_block block)
+{
+ /* dummy variant */
+ if (!v->shader)
+ return;
+
+ const struct ir3_const_state *const_state = &v->shader->const_state;
+ uint32_t base = const_state->offsets.immediate;
+ int size = const_state->immediates_count;
+
+ /* truncate size to avoid writing constants that shader
+ * does not use:
+ */
+ size = MIN2(size + base, v->constlen) - base;
+
+ if (size <= 0)
+ return;
+
+ tu_cs_emit_pkt7(cs, opcode, 3 + size * 4);
+ tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(base) |
+ CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
+ CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
+ CP_LOAD_STATE6_0_STATE_BLOCK(block) |
+ CP_LOAD_STATE6_0_NUM_UNIT(size));
+ tu_cs_emit(cs, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
+ tu_cs_emit(cs, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
+
+ for (unsigned i = 0; i < size; i++) {
+ tu_cs_emit(cs, const_state->immediates[i].val[0]);
+ tu_cs_emit(cs, const_state->immediates[i].val[1]);
+ tu_cs_emit(cs, const_state->immediates[i].val[2]);
+ tu_cs_emit(cs, const_state->immediates[i].val[3]);
+ }
+}
+
static void
tu6_emit_program(struct tu_cs *cs,
const struct tu_pipeline_builder *builder,
tu6_emit_vs_system_values(cs, vs);
tu6_emit_vpc(cs, vs, fs, binning_pass);
tu6_emit_vpc_varying_modes(cs, fs, binning_pass);
- tu6_emit_fs_system_values(cs, fs);
tu6_emit_fs_inputs(cs, fs);
tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count);
tu6_emit_shader_object(cs, MESA_SHADER_FRAGMENT, fs, binary_bo,
builder->shader_offsets[MESA_SHADER_FRAGMENT]);
+
+ tu6_emit_immediates(cs, vs, CP_LOAD_STATE6_GEOM, SB6_VS_SHADER);
+ if (!binning_pass)
+ tu6_emit_immediates(cs, fs, CP_LOAD_STATE6_FRAG, SB6_FS_SHADER);
}
static void
{
uint32_t vfd_decode_idx = 0;
- /* why do we go beyond inputs_count? */
- assert(vs->inputs_count + 1 <= MAX_VERTEX_ATTRIBS);
- for (uint32_t i = 0; i <= vs->inputs_count; i++) {
+ for (uint32_t i = 0; i < vs->inputs_count; i++) {
if (vs->inputs[i].sysval || !vs->inputs[i].compmask)
continue;
offsets[vfd_decode_idx] = vi_attr->offset;
vfd_decode_idx++;
+ assert(vfd_decode_idx <= MAX_VERTEX_ATTRIBS);
}
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_0, 1);
tu_cs_emit(cs, 0x80);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
tu_cs_emit(cs, 0x0);
- tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8004, 1);
+ tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
tu_cs_emit(cs, 0x0);
}
tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true);
pipeline->program.binning_state_ib =
tu_cs_end_sub_stream(&pipeline->cs, &prog_cs);
+
+ for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+ if (!builder->shaders[i])
+ continue;
+
+ struct tu_program_descriptor_linkage *link = &pipeline->program.link[i];
+ struct ir3_shader *shader = builder->shaders[i]->variants[0].shader;
+
+ link->ubo_state = shader->ubo_state;
+ link->const_state = shader->const_state;
+ link->constlen = builder->shaders[i]->variants[0].constlen;
+ link->texture_map = builder->shaders[i]->texture_map;
+ link->sampler_map = builder->shaders[i]->sampler_map;
+ link->ubo_map = builder->shaders[i]->ubo_map;
+ link->ssbo_map = builder->shaders[i]->ssbo_map;
+ link->image_mapping = builder->shaders[i]->variants[0].image_mapping;
+ }
}
static void
builder->use_depth_stencil_attachment =
subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED;
- assert(subpass->color_count ==
- create_info->pColorBlendState->attachmentCount);
+ assert(subpass->color_count == 0 ||
+ subpass->color_count == create_info->pColorBlendState->attachmentCount);
builder->color_attachment_count = subpass->color_count;
for (uint32_t i = 0; i < subpass->color_count; i++) {
const uint32_t a = subpass->color_attachments[i].attachment;
{
TU_FROM_HANDLE(tu_device, dev, device);
TU_FROM_HANDLE(tu_pipeline_cache, cache, pipelineCache);
+ VkResult final_result = VK_SUCCESS;
for (uint32_t i = 0; i < count; i++) {
struct tu_pipeline_builder builder;
tu_pipeline_builder_init_graphics(&builder, dev, cache,
&pCreateInfos[i], pAllocator);
- struct tu_pipeline *pipeline;
+ struct tu_pipeline *pipeline = NULL;
VkResult result = tu_pipeline_builder_build(&builder, &pipeline);
tu_pipeline_builder_finish(&builder);
- if (result != VK_SUCCESS) {
- for (uint32_t j = 0; j < i; j++) {
- tu_DestroyPipeline(device, pPipelines[j], pAllocator);
- pPipelines[j] = VK_NULL_HANDLE;
- }
-
- return result;
+ if (result == VK_SUCCESS) {
+ pPipelines[i] = tu_pipeline_to_handle(pipeline);
+ } else {
+ pPipelines[i] = NULL;
+ final_result = result;
}
-
- pPipelines[i] = tu_pipeline_to_handle(pipeline);
}
- return VK_SUCCESS;
+ return final_result;
}
static VkResult
pAllocator, &pPipelines[i]);
if (r != VK_SUCCESS) {
result = r;
- pPipelines[i] = VK_NULL_HANDLE;
}
+ pPipelines[i] = VK_NULL_HANDLE;
}
return result;
projects / mesa.git / blobdiff