#include "fd6_texture.h"
#include "fd6_format.h"
-static void
-delete_shader_stateobj(struct fd6_shader_stateobj *so)
-{
- ir3_shader_destroy(so->shader);
- free(so);
-}
-
-static struct fd6_shader_stateobj *
+static struct ir3_shader *
create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
enum shader_t type)
{
struct fd_context *ctx = fd_context(pctx);
struct ir3_compiler *compiler = ctx->screen->compiler;
- struct fd6_shader_stateobj *so = CALLOC_STRUCT(fd6_shader_stateobj);
- so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
- return so;
+ return ir3_shader_create(compiler, cso, type, &ctx->debug);
}
static void *
static void
fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
{
- struct fd6_shader_stateobj *so = hwcso;
- delete_shader_stateobj(so);
+ struct ir3_shader *so = hwcso;
+ ir3_shader_destroy(so);
}
static void *
static void
fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
{
- struct fd6_shader_stateobj *so = hwcso;
- delete_shader_stateobj(so);
+ struct ir3_shader *so = hwcso;
+ ir3_shader_destroy(so);
}
void
}
}
-#if 0
-/* TODO maybe some of this we could pre-compute once rather than having
- * so much draw-time logic?
- */
static void
-emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
+setup_stream_out(struct fd_context *ctx, const struct ir3_shader_variant *v,
struct ir3_shader_linkage *l)
{
const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
- unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
- unsigned prog[align(l->max_loc, 2) / 2];
+ struct fd6_streamout_state *tf = &fd6_context(ctx)->tf;
+
+ memset(tf, 0, sizeof(*tf));
+
+ tf->prog_count = align(l->max_loc, 2) / 2;
- memset(prog, 0, sizeof(prog));
+ debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
for (unsigned i = 0; i < strmout->num_outputs; i++) {
const struct pipe_stream_output *out = &strmout->output[i];
unsigned k = out->register_index;
unsigned idx;
- ncomp[out->output_buffer] += out->num_components;
+ tf->ncomp[out->output_buffer] += out->num_components;
/* linkage map sorted by order frag shader wants things, so
* a bit less ideal here..
unsigned off = j + out->dst_offset; /* in dwords */
if (loc & 1) {
- prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
+ tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_B_OFF(off * 4);
} else {
- prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
+ tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_A_OFF(off * 4);
}
}
}
- OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog)));
- OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
- OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE |
- COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
- COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
- COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
- COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
- OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
- OUT_RING(ring, ncomp[0]);
- OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
- OUT_RING(ring, ncomp[1]);
- OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
- OUT_RING(ring, ncomp[2]);
- OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
- OUT_RING(ring, ncomp[3]);
- OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
- OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
- for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) {
- OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
- OUT_RING(ring, prog[i]);
- }
+ tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
+ COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
+ COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
+ COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
+ COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
}
-#endif
struct stage {
const struct ir3_shader_variant *v;
for (i = 0; i < MAX_STAGES; i++) {
if (s[i].v) {
s[i].i = &s[i].v->info;
- /* constlen is in units of 4 * vec4: */
- s[i].constlen = align(s[i].v->constlen, 4) / 4;
+ s[i].constlen = align(s[i].v->constlen, 4);
/* instrlen is already in units of 16 instr.. although
* probably we should ditch that and not make the compiler
* care about instruction group size of a3xx vs a5xx
setup_stages(emit, s);
- fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
+ fssz = FOUR_QUADS;
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
OUT_RING(ring, s[FS].instrlen); /* SP_FS_INSTRLEN */
OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
- OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(s[VS].constlen, 4)) | 0x100); /* HLSQ_VS_CONSTLEN */
- OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(s[HS].constlen, 4))); /* HLSQ_HS_CONSTLEN */
- OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(s[DS].constlen, 4))); /* HLSQ_DS_CONSTLEN */
- OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(s[GS].constlen, 4))); /* HLSQ_GS_CONSTLEN */
+ OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[VS].constlen) | 0x100); /* HLSQ_VS_CONSTLEN */
+ OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(s[HS].constlen)); /* HLSQ_HS_CONSTLEN */
+ OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(s[DS].constlen)); /* HLSQ_DS_CONSTLEN */
+ OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(s[GS].constlen)); /* HLSQ_GS_CONSTLEN */
OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
- OUT_RING(ring, s[FS].constlen | 0x100); /* HLSQ_FS_CONSTLEN */
+ OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[FS].constlen) | 0x100); /* HLSQ_FS_CONSTLEN */
OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
}
-#if 0
if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
!emit->key.binning_pass) {
- emit_stream_out(ring, s[VS].v, &l);
-
- OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
- OUT_RING(ring, 0x00000000);
- } else {
- OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
- OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
+ setup_stream_out(ctx, s[VS].v, &l);
}
-#endif
for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
uint32_t reg = 0;
COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
0xff00ff00);
- fd6_context(ctx)->max_loc = l.max_loc;
-
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
COND(psize_regid != regid(63,0), 0x100));
OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
OUT_RING(ring, COND(enable_varyings, A6XX_GRAS_CNTL_VARYING) |
- COND(s[FS].v->frag_coord, A6XX_GRAS_CNTL_XCOORD |
+ COND(s[FS].v->frag_coord,
+ A6XX_GRAS_CNTL_UNK3 |
+ A6XX_GRAS_CNTL_XCOORD |
A6XX_GRAS_CNTL_YCOORD |
A6XX_GRAS_CNTL_ZCOORD |
A6XX_GRAS_CNTL_WCOORD));
OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
OUT_RING(ring, COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_VARYING |
A6XX_RB_RENDER_CONTROL0_UNK10) |
- COND(s[FS].v->frag_coord, A6XX_RB_RENDER_CONTROL0_XCOORD |
+ COND(s[FS].v->frag_coord,
+ A6XX_RB_RENDER_CONTROL0_UNK3 |
+ A6XX_RB_RENDER_CONTROL0_XCOORD |
A6XX_RB_RENDER_CONTROL0_YCOORD |
A6XX_RB_RENDER_CONTROL0_ZCOORD |
A6XX_RB_RENDER_CONTROL0_WCOORD));
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