#include "intel/compiler/brw_compiler.h"
#include "intel/compiler/brw_nir.h"
#include "iris_context.h"
+#include "nir/tgsi_to_nir.h"
-#define ALL_SAMPLERS_XYZW .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688
-#define KEY_INIT .program_string_id = ish->program_id, ALL_SAMPLERS_XYZW
-
-static struct iris_compiled_shader *
-iris_compile_vs(struct iris_context *, struct iris_uncompiled_shader *,
- const struct brw_vs_prog_key *);
-static struct iris_compiled_shader *
-iris_compile_tcs(struct iris_context *, struct iris_uncompiled_shader *,
- const struct brw_tcs_prog_key *);
-static struct iris_compiled_shader *
-iris_compile_tes(struct iris_context *, struct iris_uncompiled_shader *,
- const struct brw_tes_prog_key *);
-static struct iris_compiled_shader *
-iris_compile_gs(struct iris_context *, struct iris_uncompiled_shader *,
- const struct brw_gs_prog_key *);
-static struct iris_compiled_shader *
-iris_compile_fs(struct iris_context *, struct iris_uncompiled_shader *,
- const struct brw_wm_prog_key *, struct brw_vue_map *);
-static struct iris_compiled_shader *
-iris_compile_cs(struct iris_context *, struct iris_uncompiled_shader *,
- const struct brw_cs_prog_key *);
-
+#define KEY_INIT_NO_ID(gen) \
+ .tex.swizzles[0 ... MAX_SAMPLERS - 1] = 0x688, \
+ .tex.compressed_multisample_layout_mask = ~0, \
+ .tex.msaa_16 = (gen >= 9 ? ~0 : 0)
+#define KEY_INIT(gen) .program_string_id = ish->program_id, KEY_INIT_NO_ID(gen)
static unsigned
get_new_program_id(struct iris_screen *screen)
case nir_intrinsic_image_deref_atomic_exchange:
case nir_intrinsic_image_deref_atomic_comp_swap:
case nir_intrinsic_image_deref_size:
- case nir_intrinsic_image_deref_samples: {
+ case nir_intrinsic_image_deref_samples:
+ case nir_intrinsic_image_deref_load_raw_intel:
+ case nir_intrinsic_image_deref_store_raw_intel: {
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
nir_variable *var = nir_deref_instr_get_variable(deref);
// XXX: need unify_interfaces() at link time...
+/**
+ * Fix an uncompiled shader's stream output info.
+ *
+ * Core Gallium stores output->register_index as a "slot" number, where
+ * slots are assigned consecutively to all outputs in info->outputs_written.
+ * This naive packing of outputs doesn't work for us - we too have slots,
+ * but the layout is defined by the VUE map, which we won't have until we
+ * compile a specific shader variant. So, we remap these and simply store
+ * VARYING_SLOT_* in our copy's output->register_index fields.
+ *
+ * We also fix up VARYING_SLOT_{LAYER,VIEWPORT,PSIZ} to select the Y/Z/W
+ * components of our VUE header. See brw_vue_map.c for the layout.
+ */
static void
-update_so_info(struct pipe_stream_output_info *so_info)
+update_so_info(struct pipe_stream_output_info *so_info,
+ uint64_t outputs_written)
{
+ uint8_t reverse_map[64] = {};
+ unsigned slot = 0;
+ while (outputs_written) {
+ reverse_map[slot++] = u_bit_scan64(&outputs_written);
+ }
+
for (unsigned i = 0; i < so_info->num_outputs; i++) {
struct pipe_stream_output *output = &so_info->output[i];
+ /* Map Gallium's condensed "slots" back to real VARYING_SLOT_* enums */
+ output->register_index = reverse_map[output->register_index];
+
/* The VUE header contains three scalar fields packed together:
* - gl_PointSize is stored in VARYING_SLOT_PSIZ.w
* - gl_Layer is stored in VARYING_SLOT_PSIZ.y
}
/**
- * The pipe->create_[stage]_state() driver hooks.
- *
- * Performs basic NIR preprocessing, records any state dependencies, and
- * returns an iris_uncompiled_shader as the Gallium CSO.
+ * Sets up the starting offsets for the groups of binding table entries
+ * common to all pipeline stages.
*
- * Actual shader compilation to assembly happens later, at first use.
+ * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
+ * unused but also make sure that addition of small offsets to them will
+ * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
*/
-static void *
-iris_create_uncompiled_shader(struct pipe_context *ctx,
- nir_shader *nir,
- const struct pipe_stream_output_info *so_info)
+static uint32_t
+assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
+ const struct nir_shader *nir,
+ struct brw_stage_prog_data *prog_data,
+ uint32_t next_binding_table_offset,
+ unsigned num_system_values,
+ unsigned num_cbufs)
{
- struct iris_screen *screen = (struct iris_screen *)ctx->screen;
- const struct gen_device_info *devinfo = &screen->devinfo;
-
- struct iris_uncompiled_shader *ish =
- calloc(1, sizeof(struct iris_uncompiled_shader));
- if (!ish)
- return NULL;
+ const struct shader_info *info = &nir->info;
- nir = brw_preprocess_nir(screen->compiler, nir);
+ unsigned num_textures = util_last_bit(info->textures_used);
- NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo);
- NIR_PASS_V(nir, iris_lower_storage_image_derefs);
+ if (num_textures) {
+ prog_data->binding_table.texture_start = next_binding_table_offset;
+ prog_data->binding_table.gather_texture_start = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
+ } else {
+ prog_data->binding_table.texture_start = 0xd0d0d0d0;
+ prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
+ }
- ish->program_id = get_new_program_id(screen);
- ish->nir = nir;
- if (so_info) {
- memcpy(&ish->stream_output, so_info, sizeof(*so_info));
- update_so_info(&ish->stream_output);
+ if (info->num_images) {
+ prog_data->binding_table.image_start = next_binding_table_offset;
+ next_binding_table_offset += info->num_images;
+ } else {
+ prog_data->binding_table.image_start = 0xd0d0d0d0;
}
- return ish;
-}
+ if (num_cbufs) {
+ //assert(info->num_ubos <= BRW_MAX_UBO);
+ prog_data->binding_table.ubo_start = next_binding_table_offset;
+ next_binding_table_offset += num_cbufs;
+ } else {
+ prog_data->binding_table.ubo_start = 0xd0d0d0d0;
+ }
-static struct iris_uncompiled_shader *
-iris_create_shader_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
-{
- assert(state->type == PIPE_SHADER_IR_NIR);
+ if (info->num_ssbos || info->num_abos) {
+ prog_data->binding_table.ssbo_start = next_binding_table_offset;
+ // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
+ next_binding_table_offset += IRIS_MAX_ABOS + info->num_ssbos;
+ } else {
+ prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
+ }
- return iris_create_uncompiled_shader(ctx, state->ir.nir,
- &state->stream_output);
-}
+ prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
-static void *
-iris_create_vs_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
-{
- struct iris_context *ice = (void *) ctx;
- struct iris_screen *screen = (void *) ctx->screen;
- struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
+ /* Plane 0 is just the regular texture section */
+ prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
- /* User clip planes */
- if (ish->nir->info.clip_distance_array_size == 0)
- ish->nos |= (1ull << IRIS_NOS_RASTERIZER);
+ prog_data->binding_table.plane_start[1] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
- if (screen->precompile) {
- struct brw_vs_prog_key key = { KEY_INIT };
+ prog_data->binding_table.plane_start[2] = next_binding_table_offset;
+ next_binding_table_offset += num_textures;
- iris_compile_vs(ice, ish, &key);
- }
+ /* Set the binding table size */
+ prog_data->binding_table.size_bytes = next_binding_table_offset * 4;
- return ish;
+ return next_binding_table_offset;
}
-static void *
-iris_create_tcs_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
+static void
+setup_vec4_image_sysval(uint32_t *sysvals, uint32_t idx,
+ unsigned offset, unsigned n)
{
- struct iris_context *ice = (void *) ctx;
- struct iris_screen *screen = (void *) ctx->screen;
- struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
- struct shader_info *info = &ish->nir->info;
-
- // XXX: NOS?
-
- if (screen->precompile) {
- const unsigned _GL_TRIANGLES = 0x0004;
- struct brw_tcs_prog_key key = {
- KEY_INIT,
- // XXX: make sure the linker fills this out from the TES...
- .tes_primitive_mode =
- info->tess.primitive_mode ? info->tess.primitive_mode
- : _GL_TRIANGLES,
- .outputs_written = info->outputs_written,
- .patch_outputs_written = info->patch_outputs_written,
- };
+ assert(offset % sizeof(uint32_t) == 0);
- iris_compile_tcs(ice, ish, &key);
- }
+ for (unsigned i = 0; i < n; ++i)
+ sysvals[i] = BRW_PARAM_IMAGE(idx, offset / sizeof(uint32_t) + i);
- return ish;
+ for (unsigned i = n; i < 4; ++i)
+ sysvals[i] = BRW_PARAM_BUILTIN_ZERO;
}
-static void *
-iris_create_tes_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
+/**
+ * Associate NIR uniform variables with the prog_data->param[] mechanism
+ * used by the backend. Also, decide which UBOs we'd like to push in an
+ * ideal situation (though the backend can reduce this).
+ */
+static void
+iris_setup_uniforms(const struct brw_compiler *compiler,
+ void *mem_ctx,
+ nir_shader *nir,
+ struct brw_stage_prog_data *prog_data,
+ enum brw_param_builtin **out_system_values,
+ unsigned *out_num_system_values,
+ unsigned *out_num_cbufs)
{
- struct iris_context *ice = (void *) ctx;
- struct iris_screen *screen = (void *) ctx->screen;
- struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
- struct shader_info *info = &ish->nir->info;
-
- // XXX: NOS?
+ const struct gen_device_info *devinfo = compiler->devinfo;
- if (screen->precompile) {
- struct brw_tes_prog_key key = {
- KEY_INIT,
- // XXX: not ideal, need TCS output/TES input unification
- .inputs_read = info->inputs_read,
- .patch_inputs_read = info->patch_inputs_read,
- };
-
- iris_compile_tes(ice, ish, &key);
- }
+ /* The intel compiler assumes that num_uniforms is in bytes. For
+ * scalar that means 4 bytes per uniform slot.
+ *
+ * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
+ */
+ nir->num_uniforms *= 4;
- return ish;
-}
+ const unsigned IRIS_MAX_SYSTEM_VALUES =
+ PIPE_MAX_SHADER_IMAGES * BRW_IMAGE_PARAM_SIZE;
+ enum brw_param_builtin *system_values =
+ rzalloc_array(mem_ctx, enum brw_param_builtin, IRIS_MAX_SYSTEM_VALUES);
+ unsigned num_system_values = 0;
-static void *
-iris_create_gs_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
-{
- struct iris_context *ice = (void *) ctx;
- struct iris_screen *screen = (void *) ctx->screen;
- struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
+ unsigned patch_vert_idx = -1;
+ unsigned ucp_idx[IRIS_MAX_CLIP_PLANES];
+ unsigned img_idx[PIPE_MAX_SHADER_IMAGES];
+ memset(ucp_idx, -1, sizeof(ucp_idx));
+ memset(img_idx, -1, sizeof(img_idx));
- // XXX: NOS?
+ nir_function_impl *impl = nir_shader_get_entrypoint(nir);
- if (screen->precompile) {
- struct brw_gs_prog_key key = { KEY_INIT };
+ nir_builder b;
+ nir_builder_init(&b, impl);
- iris_compile_gs(ice, ish, &key);
- }
+ b.cursor = nir_before_block(nir_start_block(impl));
+ nir_ssa_def *temp_ubo_name = nir_ssa_undef(&b, 1, 32);
- return ish;
-}
+ /* Turn system value intrinsics into uniforms */
+ nir_foreach_block(block, impl) {
+ nir_foreach_instr_safe(instr, block) {
+ if (instr->type != nir_instr_type_intrinsic)
+ continue;
-static void *
-iris_create_fs_state(struct pipe_context *ctx,
- const struct pipe_shader_state *state)
-{
- struct iris_context *ice = (void *) ctx;
- struct iris_screen *screen = (void *) ctx->screen;
- struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
- struct shader_info *info = &ish->nir->info;
+ nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+ nir_ssa_def *offset;
- ish->nos |= (1ull << IRIS_NOS_FRAMEBUFFER) |
- (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA) |
- (1ull << IRIS_NOS_RASTERIZER) |
- (1ull << IRIS_NOS_BLEND);
+ switch (intrin->intrinsic) {
+ case nir_intrinsic_load_user_clip_plane: {
+ unsigned ucp = nir_intrinsic_ucp_id(intrin);
- /* The program key needs the VUE map if there are > 16 inputs */
- if (util_bitcount64(ish->nir->info.inputs_read &
- BRW_FS_VARYING_INPUT_MASK) > 16) {
- ish->nos |= (1ull << IRIS_NOS_LAST_VUE_MAP);
- }
+ if (ucp_idx[ucp] == -1) {
+ ucp_idx[ucp] = num_system_values;
+ num_system_values += 4;
+ }
- if (screen->precompile) {
- const uint64_t color_outputs = info->outputs_written &
- ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH) |
- BITFIELD64_BIT(FRAG_RESULT_STENCIL) |
- BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK));
+ for (int i = 0; i < 4; i++) {
+ system_values[ucp_idx[ucp] + i] =
+ BRW_PARAM_BUILTIN_CLIP_PLANE(ucp, i);
+ }
- bool can_rearrange_varyings =
- util_bitcount64(info->inputs_read & BRW_FS_VARYING_INPUT_MASK) <= 16;
+ b.cursor = nir_before_instr(instr);
+ offset = nir_imm_int(&b, ucp_idx[ucp] * sizeof(uint32_t));
+ break;
+ }
+ case nir_intrinsic_load_patch_vertices_in:
+ if (patch_vert_idx == -1)
+ patch_vert_idx = num_system_values++;
- struct brw_wm_prog_key key = {
- KEY_INIT,
- .nr_color_regions = util_bitcount(color_outputs),
- .coherent_fb_fetch = true,
- .input_slots_valid =
- can_rearrange_varyings ? 0 : info->inputs_read | VARYING_BIT_POS,
- };
+ system_values[patch_vert_idx] =
+ BRW_PARAM_BUILTIN_PATCH_VERTICES_IN;
- iris_compile_fs(ice, ish, &key, NULL);
- }
+ b.cursor = nir_before_instr(instr);
+ offset = nir_imm_int(&b, patch_vert_idx * sizeof(uint32_t));
+ break;
+ case nir_intrinsic_image_deref_load_param_intel: {
+ assert(devinfo->gen < 9);
+ nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
+ nir_variable *var = nir_deref_instr_get_variable(deref);
- return ish;
-}
+ /* XXX: var->data.binding is not set properly. We need to run
+ * some form of gl_nir_lower_samplers_as_deref() to get it.
+ * This breaks tests which use more than one image.
+ */
+ if (img_idx[var->data.binding] == -1) {
+ /* GL only allows arrays of arrays of images. */
+ assert(glsl_type_is_image(glsl_without_array(var->type)));
+ unsigned num_images = MAX2(1, glsl_get_aoa_size(var->type));
+
+ for (int i = 0; i < num_images; i++) {
+ const unsigned img = var->data.binding + i;
+
+ img_idx[img] = num_system_values;
+ num_system_values += BRW_IMAGE_PARAM_SIZE;
+
+ uint32_t *img_sv = &system_values[img_idx[img]];
+
+ setup_vec4_image_sysval(
+ img_sv + BRW_IMAGE_PARAM_OFFSET_OFFSET, img,
+ offsetof(struct brw_image_param, offset), 2);
+ setup_vec4_image_sysval(
+ img_sv + BRW_IMAGE_PARAM_SIZE_OFFSET, img,
+ offsetof(struct brw_image_param, size), 3);
+ setup_vec4_image_sysval(
+ img_sv + BRW_IMAGE_PARAM_STRIDE_OFFSET, img,
+ offsetof(struct brw_image_param, stride), 4);
+ setup_vec4_image_sysval(
+ img_sv + BRW_IMAGE_PARAM_TILING_OFFSET, img,
+ offsetof(struct brw_image_param, tiling), 3);
+ setup_vec4_image_sysval(
+ img_sv + BRW_IMAGE_PARAM_SWIZZLING_OFFSET, img,
+ offsetof(struct brw_image_param, swizzling), 2);
+ }
+ }
-static void *
-iris_create_compute_state(struct pipe_context *ctx,
- const struct pipe_compute_state *state)
-{
- assert(state->ir_type == PIPE_SHADER_IR_NIR);
+ b.cursor = nir_before_instr(instr);
+ offset = nir_iadd(&b,
+ get_aoa_deref_offset(&b, deref, BRW_IMAGE_PARAM_SIZE * 4),
+ nir_imm_int(&b, img_idx[var->data.binding] * 4 +
+ nir_intrinsic_base(intrin) * 16));
+ break;
+ }
+ default:
+ continue;
+ }
- struct iris_context *ice = (void *) ctx;
- struct iris_screen *screen = (void *) ctx->screen;
- struct iris_uncompiled_shader *ish =
- iris_create_uncompiled_shader(ctx, (void *) state->prog, NULL);
-
- // XXX: disallow more than 64KB of shared variables
-
- if (screen->precompile) {
- struct brw_cs_prog_key key = { KEY_INIT };
-
- iris_compile_cs(ice, ish, &key);
- }
-
- return ish;
-}
-
-/**
- * The pipe->delete_[stage]_state() driver hooks.
- *
- * Frees the iris_uncompiled_shader.
- */
-static void
-iris_delete_shader_state(struct pipe_context *ctx, void *state)
-{
- struct iris_uncompiled_shader *ish = state;
-
- ralloc_free(ish->nir);
- free(ish);
-}
-
-/**
- * The pipe->bind_[stage]_state() driver hook.
- *
- * Binds an uncompiled shader as the current one for a particular stage.
- * Updates dirty tracking to account for the shader's NOS.
- */
-static void
-bind_state(struct iris_context *ice,
- struct iris_uncompiled_shader *ish,
- gl_shader_stage stage)
-{
- uint64_t dirty_bit = IRIS_DIRTY_UNCOMPILED_VS << stage;
- const uint64_t nos = ish ? ish->nos : 0;
-
- ice->shaders.uncompiled[stage] = ish;
- ice->state.dirty |= dirty_bit;
-
- /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
- * (or that they no longer need to do so).
- */
- for (int i = 0; i < IRIS_NOS_COUNT; i++) {
- if (nos & (1 << i))
- ice->state.dirty_for_nos[i] |= dirty_bit;
- else
- ice->state.dirty_for_nos[i] &= ~dirty_bit;
- }
-}
-
-static void
-iris_bind_vs_state(struct pipe_context *ctx, void *state)
-{
- bind_state((void *) ctx, state, MESA_SHADER_VERTEX);
-}
-
-static void
-iris_bind_tcs_state(struct pipe_context *ctx, void *state)
-{
- bind_state((void *) ctx, state, MESA_SHADER_TESS_CTRL);
-}
-
-static void
-iris_bind_tes_state(struct pipe_context *ctx, void *state)
-{
- struct iris_context *ice = (struct iris_context *)ctx;
-
- /* Enabling/disabling optional stages requires a URB reconfiguration. */
- if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
- ice->state.dirty |= IRIS_DIRTY_URB;
-
- bind_state((void *) ctx, state, MESA_SHADER_TESS_EVAL);
-}
-
-static void
-iris_bind_gs_state(struct pipe_context *ctx, void *state)
-{
- struct iris_context *ice = (struct iris_context *)ctx;
-
- /* Enabling/disabling optional stages requires a URB reconfiguration. */
- if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
- ice->state.dirty |= IRIS_DIRTY_URB;
-
- bind_state((void *) ctx, state, MESA_SHADER_GEOMETRY);
-}
-
-static void
-iris_bind_fs_state(struct pipe_context *ctx, void *state)
-{
- bind_state((void *) ctx, state, MESA_SHADER_FRAGMENT);
-}
-
-static void
-iris_bind_cs_state(struct pipe_context *ctx, void *state)
-{
- bind_state((void *) ctx, state, MESA_SHADER_COMPUTE);
-}
-
-/**
- * Sets up the starting offsets for the groups of binding table entries
- * common to all pipeline stages.
- *
- * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
- * unused but also make sure that addition of small offsets to them will
- * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
- */
-static uint32_t
-assign_common_binding_table_offsets(const struct gen_device_info *devinfo,
- const struct nir_shader *nir,
- struct brw_stage_prog_data *prog_data,
- uint32_t next_binding_table_offset,
- unsigned num_system_values)
-{
- const struct shader_info *info = &nir->info;
-
- if (info->num_textures) {
- prog_data->binding_table.texture_start = next_binding_table_offset;
- prog_data->binding_table.gather_texture_start = next_binding_table_offset;
- next_binding_table_offset += info->num_textures;
- } else {
- prog_data->binding_table.texture_start = 0xd0d0d0d0;
- prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
- }
-
- if (info->num_images) {
- prog_data->binding_table.image_start = next_binding_table_offset;
- next_binding_table_offset += info->num_images;
- } else {
- prog_data->binding_table.image_start = 0xd0d0d0d0;
- }
-
- int num_ubos = info->num_ubos +
- ((nir->num_uniforms || num_system_values) ? 1 : 0);
-
- if (num_ubos) {
- //assert(info->num_ubos <= BRW_MAX_UBO);
- prog_data->binding_table.ubo_start = next_binding_table_offset;
- next_binding_table_offset += num_ubos;
- } else {
- prog_data->binding_table.ubo_start = 0xd0d0d0d0;
- }
-
- if (info->num_ssbos || info->num_abos) {
- prog_data->binding_table.ssbo_start = next_binding_table_offset;
- // XXX: see iris_state "wasting 16 binding table slots for ABOs" comment
- next_binding_table_offset += IRIS_MAX_ABOS + info->num_ssbos;
- } else {
- prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
- }
-
- prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
-
- /* Plane 0 is just the regular texture section */
- prog_data->binding_table.plane_start[0] = prog_data->binding_table.texture_start;
-
- prog_data->binding_table.plane_start[1] = next_binding_table_offset;
- next_binding_table_offset += info->num_textures;
-
- prog_data->binding_table.plane_start[2] = next_binding_table_offset;
- next_binding_table_offset += info->num_textures;
-
- /* Set the binding table size */
- prog_data->binding_table.size_bytes = next_binding_table_offset * 4;
-
- return next_binding_table_offset;
-}
-
-/**
- * Associate NIR uniform variables with the prog_data->param[] mechanism
- * used by the backend. Also, decide which UBOs we'd like to push in an
- * ideal situation (though the backend can reduce this).
- */
-static void
-iris_setup_uniforms(const struct brw_compiler *compiler,
- void *mem_ctx,
- nir_shader *nir,
- struct brw_stage_prog_data *prog_data,
- enum brw_param_builtin **out_system_values,
- unsigned *out_num_system_values)
-{
- /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
- * about it for compute shaders, so go ahead and make some fake ones
- * which the backend will dead code eliminate.
- */
- prog_data->nr_params = nir->num_uniforms;
- prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
-
- /* The intel compiler assumes that num_uniforms is in bytes. For
- * scalar that means 4 bytes per uniform slot.
- *
- * Ref: brw_nir_lower_uniforms, type_size_scalar_bytes.
- */
- nir->num_uniforms *= 4;
-
- const unsigned IRIS_MAX_SYSTEM_VALUES = 32;
- enum brw_param_builtin *system_values =
- rzalloc_array(mem_ctx, enum brw_param_builtin, IRIS_MAX_SYSTEM_VALUES);
- unsigned num_system_values = 0;
-
- nir_function_impl *impl = nir_shader_get_entrypoint(nir);
-
- nir_builder b;
- nir_builder_init(&b, impl);
-
- b.cursor = nir_before_block(nir_start_block(impl));
- nir_ssa_def *temp_ubo_name = nir_ssa_undef(&b, 1, 32);
-
- /* Turn system value intrinsics into uniforms */
- nir_foreach_block(block, impl) {
- nir_foreach_instr_safe(instr, block) {
- if (instr->type != nir_instr_type_intrinsic)
- continue;
-
- nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-
- unsigned idx = num_system_values;
-
- switch (intrin->intrinsic) {
- case nir_intrinsic_load_user_clip_plane: {
- unsigned ucp = nir_intrinsic_ucp_id(intrin);
- for (int i = 0; i < 4; i++) {
- system_values[num_system_values++] =
- BRW_PARAM_BUILTIN_CLIP_PLANE(ucp, i);
- }
- break;
- }
- case nir_intrinsic_load_patch_vertices_in:
- system_values[num_system_values++] =
- BRW_PARAM_BUILTIN_PATCH_VERTICES_IN;
- break;
- default:
- continue;
- }
-
- b.cursor = nir_before_instr(instr);
-
- unsigned comps = nir_intrinsic_dest_components(intrin);
- nir_ssa_def *offset = nir_imm_int(&b, idx * sizeof(uint32_t));
+ unsigned comps = nir_intrinsic_dest_components(intrin);
nir_intrinsic_instr *load =
nir_intrinsic_instr_create(nir, nir_intrinsic_load_ubo);
nir_validate_shader(nir, "after remap");
- // XXX: vs clip planes?
if (nir->info.stage != MESA_SHADER_COMPUTE)
brw_nir_analyze_ubo_ranges(compiler, nir, NULL, prog_data->ubo_ranges);
+ /* We don't use params[], but fs_visitor::nir_setup_uniforms() asserts
+ * about it for compute shaders, so go ahead and make some fake ones
+ * which the backend will dead code eliminate.
+ */
+ prog_data->nr_params = nir->num_uniforms / 4;
+ prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
+
+ /* System values and uniforms are stored in constant buffer 0, the
+ * user-facing UBOs are indexed by one. So if any constant buffer is
+ * needed, the constant buffer 0 will be needed, so account for it.
+ */
+ unsigned num_cbufs = nir->info.num_ubos;
+ if (num_cbufs || num_system_values || nir->num_uniforms)
+ num_cbufs++;
+
*out_system_values = system_values;
*out_num_system_values = num_system_values;
+ *out_num_cbufs = num_cbufs;
}
/**
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
enum brw_param_builtin *system_values;
unsigned num_system_values;
+ unsigned num_cbufs;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
nir_shader_gather_info(nir, impl);
}
- // XXX: alt mode
+ if (nir->info.name && strncmp(nir->info.name, "ARB", 3) == 0)
+ prog_data->use_alt_mode = true;
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
- &num_system_values);
+ &num_system_values, &num_cbufs);
assign_common_binding_table_offsets(devinfo, nir, prog_data, 0,
- num_system_values);
+ num_system_values, num_cbufs);
brw_compute_vue_map(devinfo,
&vue_prog_data->vue_map, nir->info.outputs_written,
struct iris_compiled_shader *shader =
iris_upload_shader(ice, IRIS_CACHE_VS, sizeof(*key), key, program,
- prog_data, so_decls, system_values, num_system_values);
+ prog_data, so_decls, system_values, num_system_values,
+ num_cbufs);
if (ish->compiled_once) {
perf_debug(&ice->dbg, "Recompiling vertex shader\n");
{
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_VERTEX];
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_vs_prog_key key = { KEY_INIT };
+ struct brw_vs_prog_key key = { KEY_INIT(devinfo->gen) };
ice->vtbl.populate_vs_key(ice, &ish->nir->info, &key);
struct iris_compiled_shader *old = ice->shaders.prog[IRIS_CACHE_VS];
IRIS_DIRTY_BINDINGS_VS |
IRIS_DIRTY_CONSTANTS_VS |
IRIS_DIRTY_VF_SGVS;
+ const struct brw_vs_prog_data *vs_prog_data =
+ (void *) shader->prog_data;
+ const bool uses_draw_params = vs_prog_data->uses_firstvertex ||
+ vs_prog_data->uses_baseinstance;
+ const bool uses_derived_draw_params = vs_prog_data->uses_drawid ||
+ vs_prog_data->uses_is_indexed_draw;
+ const bool needs_sgvs_element = uses_draw_params ||
+ vs_prog_data->uses_instanceid ||
+ vs_prog_data->uses_vertexid;
+ bool needs_edge_flag = false;
+ nir_foreach_variable(var, &ish->nir->inputs) {
+ if (var->data.location == VERT_ATTRIB_EDGEFLAG)
+ needs_edge_flag = true;
+ }
+
+ if (ice->state.vs_uses_draw_params != uses_draw_params ||
+ ice->state.vs_uses_derived_draw_params != uses_derived_draw_params ||
+ ice->state.vs_needs_edge_flag != needs_edge_flag) {
+ ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
+ IRIS_DIRTY_VERTEX_ELEMENTS;
+ }
+ ice->state.vs_uses_draw_params = uses_draw_params;
+ ice->state.vs_uses_derived_draw_params = uses_derived_draw_params;
+ ice->state.vs_needs_sgvs_element = needs_sgvs_element;
+ ice->state.vs_needs_edge_flag = needs_edge_flag;
}
}
return &nir->info;
}
-// XXX: this function is gross
-unsigned
-iris_get_shader_num_ubos(const struct iris_context *ice, gl_shader_stage stage)
-{
- const struct iris_uncompiled_shader *ish = ice->shaders.uncompiled[stage];
- const struct iris_compiled_shader *shader = ice->shaders.prog[stage];
-
- if (ish) {
- const nir_shader *nir = ish->nir;
- /* see assign_common_binding_table_offsets */
- return nir->info.num_ubos +
- ((nir->num_uniforms || shader->num_system_values) ? 1 : 0);
- }
- return 0;
-}
-
/**
* Get the union of TCS output and TES input slots.
*
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
enum brw_param_builtin *system_values = NULL;
unsigned num_system_values = 0;
+ unsigned num_cbufs;
nir_shader *nir;
nir = nir_shader_clone(mem_ctx, ish->nir);
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
- &num_system_values);
+ &num_system_values, &num_cbufs);
assign_common_binding_table_offsets(devinfo, nir, prog_data, 0,
- num_system_values);
+ num_system_values, num_cbufs);
} else {
nir = brw_nir_create_passthrough_tcs(mem_ctx, compiler, options, key);
/* Reserve space for passing the default tess levels as constants. */
- prog_data->param = rzalloc_array(mem_ctx, uint32_t, 8);
- prog_data->nr_params = 8;
+ num_system_values = 8;
+ system_values =
+ rzalloc_array(mem_ctx, enum brw_param_builtin, num_system_values);
+ prog_data->param = rzalloc_array(mem_ctx, uint32_t, num_system_values);
+ prog_data->nr_params = num_system_values;
+
+ if (key->tes_primitive_mode == GL_QUADS) {
+ for (int i = 0; i < 4; i++)
+ system_values[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
+
+ system_values[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
+ system_values[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y;
+ } else if (key->tes_primitive_mode == GL_TRIANGLES) {
+ for (int i = 0; i < 3; i++)
+ system_values[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
+
+ system_values[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
+ } else {
+ assert(key->tes_primitive_mode == GL_ISOLINES);
+ system_values[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y;
+ system_values[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X;
+ }
+
prog_data->ubo_ranges[0].length = 1;
}
struct iris_compiled_shader *shader =
iris_upload_shader(ice, IRIS_CACHE_TCS, sizeof(*key), key, program,
- prog_data, NULL, system_values, num_system_values);
+ prog_data, NULL, system_values, num_system_values,
+ num_cbufs);
if (ish) {
if (ish->compiled_once) {
{
struct iris_uncompiled_shader *tcs =
ice->shaders.uncompiled[MESA_SHADER_TESS_CTRL];
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
const struct shader_info *tes_info =
iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
struct brw_tcs_prog_key key = {
- ALL_SAMPLERS_XYZW,
+ KEY_INIT_NO_ID(devinfo->gen),
.program_string_id = tcs ? tcs->program_id : 0,
.tes_primitive_mode = tes_info->tess.primitive_mode,
.input_vertices = ice->state.vertices_per_patch,
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
enum brw_param_builtin *system_values;
unsigned num_system_values;
+ unsigned num_cbufs;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
- &num_system_values);
+ &num_system_values, &num_cbufs);
assign_common_binding_table_offsets(devinfo, nir, prog_data, 0,
- num_system_values);
+ num_system_values, num_cbufs);
struct brw_vue_map input_vue_map;
brw_compute_tess_vue_map(&input_vue_map, key->inputs_read,
struct iris_compiled_shader *shader =
iris_upload_shader(ice, IRIS_CACHE_TES, sizeof(*key), key, program,
- prog_data, so_decls, system_values, num_system_values);
+ prog_data, so_decls, system_values, num_system_values,
+ num_cbufs);
if (ish->compiled_once) {
perf_debug(&ice->dbg, "Recompiling tessellation evaluation shader\n");
{
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL];
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
- struct brw_tes_prog_key key = { KEY_INIT };
+ struct brw_tes_prog_key key = { KEY_INIT(devinfo->gen) };
get_unified_tess_slots(ice, &key.inputs_read, &key.patch_inputs_read);
ice->vtbl.populate_tes_key(ice, &key);
IRIS_DIRTY_BINDINGS_TES |
IRIS_DIRTY_CONSTANTS_TES;
}
+
+ /* TODO: Could compare and avoid flagging this. */
+ const struct shader_info *tes_info = &ish->nir->info;
+ if (tes_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) {
+ ice->state.dirty |= IRIS_DIRTY_CONSTANTS_TES;
+ ice->state.shaders[MESA_SHADER_TESS_EVAL].cbuf0_needs_upload = true;
+ }
}
/**
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
enum brw_param_builtin *system_values;
unsigned num_system_values;
+ unsigned num_cbufs;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
- &num_system_values);
+ &num_system_values, &num_cbufs);
assign_common_binding_table_offsets(devinfo, nir, prog_data, 0,
- num_system_values);
+ num_system_values, num_cbufs);
brw_compute_vue_map(devinfo,
&vue_prog_data->vue_map, nir->info.outputs_written,
struct iris_compiled_shader *shader =
iris_upload_shader(ice, IRIS_CACHE_GS, sizeof(*key), key, program,
- prog_data, so_decls, system_values, num_system_values);
+ prog_data, so_decls, system_values, num_system_values,
+ num_cbufs);
if (ish->compiled_once) {
perf_debug(&ice->dbg, "Recompiling geometry shader\n");
struct iris_compiled_shader *shader = NULL;
if (ish) {
- struct brw_gs_prog_key key = { KEY_INIT };
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_gs_prog_key key = { KEY_INIT(devinfo->gen) };
ice->vtbl.populate_gs_key(ice, &key);
shader =
struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
enum brw_param_builtin *system_values;
unsigned num_system_values;
+ unsigned num_cbufs;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
- // XXX: alt mode
+ if (nir->info.name && strncmp(nir->info.name, "ARB", 3) == 0)
+ prog_data->use_alt_mode = true;
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
- &num_system_values);
+ &num_system_values, &num_cbufs);
assign_common_binding_table_offsets(devinfo, nir, prog_data,
MAX2(key->nr_color_regions, 1),
- num_system_values);
+ num_system_values, num_cbufs);
char *error_str = NULL;
const unsigned *program =
brw_compile_fs(compiler, &ice->dbg, mem_ctx, key, fs_prog_data,
struct iris_compiled_shader *shader =
iris_upload_shader(ice, IRIS_CACHE_FS, sizeof(*key), key, program,
- prog_data, NULL, system_values, num_system_values);
+ prog_data, NULL, system_values, num_system_values,
+ num_cbufs);
if (ish->compiled_once) {
perf_debug(&ice->dbg, "Recompiling fragment shader\n");
{
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
- struct brw_wm_prog_key key = { KEY_INIT };
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_wm_prog_key key = { KEY_INIT(devinfo->gen) };
ice->vtbl.populate_fs_key(ice, &key);
if (ish->nos & (1ull << IRIS_NOS_LAST_VUE_MAP))
struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
enum brw_param_builtin *system_values;
unsigned num_system_values;
+ unsigned num_cbufs;
nir_shader *nir = nir_shader_clone(mem_ctx, ish->nir);
prog_data->total_shared = nir->info.cs.shared_size;
iris_setup_uniforms(compiler, mem_ctx, nir, prog_data, &system_values,
- &num_system_values);
+ &num_system_values, &num_cbufs);
assign_common_binding_table_offsets(devinfo, nir, prog_data, 1,
- num_system_values);
+ num_system_values, num_cbufs);
char *error_str = NULL;
const unsigned *program =
struct iris_compiled_shader *shader =
iris_upload_shader(ice, IRIS_CACHE_CS, sizeof(*key), key, program,
- prog_data, NULL, system_values, num_system_values);
+ prog_data, NULL, system_values, num_system_values,
+ num_cbufs);
if (ish->compiled_once) {
perf_debug(&ice->dbg, "Recompiling compute shader\n");
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_COMPUTE];
- struct brw_cs_prog_key key = { KEY_INIT };
+ struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_cs_prog_key key = { KEY_INIT(devinfo->gen) };
ice->vtbl.populate_cs_key(ice, &key);
struct iris_compiled_shader *old = ice->shaders.prog[IRIS_CACHE_CS];
/**
* Allocate scratch BOs as needed for the given per-thread size and stage.
- *
- * Returns the 32-bit "Scratch Space Base Pointer" value.
*/
-uint32_t
+struct iris_bo *
iris_get_scratch_space(struct iris_context *ice,
unsigned per_thread_scratch,
gl_shader_stage stage)
/* The documentation for 3DSTATE_PS "Scratch Space Base Pointer" says:
*
- * "Scratch Space per slice is computed based on 4 sub-slices. SW must
- * allocate scratch space enough so that each slice has 4 slices
- * allowed."
+ * "Scratch Space per slice is computed based on 4 sub-slices. SW
+ * must allocate scratch space enough so that each slice has 4
+ * slices allowed."
*
* According to the other driver team, this applies to compute shaders
* as well. This is not currently documented at all.
+ *
+ * This hack is no longer necessary on Gen11+.
*/
- unsigned subslice_total = 4 * devinfo->num_slices;
+ unsigned subslice_total = screen->subslice_total;
+ if (devinfo->gen < 11)
+ subslice_total = 4 * devinfo->num_slices;
assert(subslice_total >= screen->subslice_total);
if (!*bop) {
*bop = iris_bo_alloc(bufmgr, "scratch", size, IRIS_MEMZONE_SHADER);
}
- return (*bop)->gtt_offset;
+ return *bop;
+}
+
+/* ------------------------------------------------------------------- */
+
+/**
+ * The pipe->create_[stage]_state() driver hooks.
+ *
+ * Performs basic NIR preprocessing, records any state dependencies, and
+ * returns an iris_uncompiled_shader as the Gallium CSO.
+ *
+ * Actual shader compilation to assembly happens later, at first use.
+ */
+static void *
+iris_create_uncompiled_shader(struct pipe_context *ctx,
+ nir_shader *nir,
+ const struct pipe_stream_output_info *so_info)
+{
+ struct iris_screen *screen = (struct iris_screen *)ctx->screen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
+
+ struct iris_uncompiled_shader *ish =
+ calloc(1, sizeof(struct iris_uncompiled_shader));
+ if (!ish)
+ return NULL;
+
+ nir = brw_preprocess_nir(screen->compiler, nir, NULL);
+
+ NIR_PASS_V(nir, brw_nir_lower_image_load_store, devinfo);
+ NIR_PASS_V(nir, iris_lower_storage_image_derefs);
+
+ ish->program_id = get_new_program_id(screen);
+ ish->nir = nir;
+ if (so_info) {
+ memcpy(&ish->stream_output, so_info, sizeof(*so_info));
+ update_so_info(&ish->stream_output, nir->info.outputs_written);
+ }
+
+ return ish;
+}
+
+static struct iris_uncompiled_shader *
+iris_create_shader_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct nir_shader *nir;
+
+ if (state->type == PIPE_SHADER_IR_TGSI)
+ nir = tgsi_to_nir(state->tokens, ctx->screen);
+ else
+ nir = state->ir.nir;
+
+ return iris_create_uncompiled_shader(ctx, nir, &state->stream_output);
+}
+
+static void *
+iris_create_vs_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct iris_context *ice = (void *) ctx;
+ struct iris_screen *screen = (void *) ctx->screen;
+ struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
+
+ /* User clip planes */
+ if (ish->nir->info.clip_distance_array_size == 0)
+ ish->nos |= (1ull << IRIS_NOS_RASTERIZER);
+
+ if (screen->precompile) {
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_vs_prog_key key = { KEY_INIT(devinfo->gen) };
+
+ iris_compile_vs(ice, ish, &key);
+ }
+
+ return ish;
+}
+
+static void *
+iris_create_tcs_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct iris_context *ice = (void *) ctx;
+ struct iris_screen *screen = (void *) ctx->screen;
+ struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
+ struct shader_info *info = &ish->nir->info;
+
+ // XXX: NOS?
+
+ if (screen->precompile) {
+ const unsigned _GL_TRIANGLES = 0x0004;
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_tcs_prog_key key = {
+ KEY_INIT(devinfo->gen),
+ // XXX: make sure the linker fills this out from the TES...
+ .tes_primitive_mode =
+ info->tess.primitive_mode ? info->tess.primitive_mode
+ : _GL_TRIANGLES,
+ .outputs_written = info->outputs_written,
+ .patch_outputs_written = info->patch_outputs_written,
+ };
+
+ iris_compile_tcs(ice, ish, &key);
+ }
+
+ return ish;
+}
+
+static void *
+iris_create_tes_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct iris_context *ice = (void *) ctx;
+ struct iris_screen *screen = (void *) ctx->screen;
+ struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
+ struct shader_info *info = &ish->nir->info;
+
+ // XXX: NOS?
+
+ if (screen->precompile) {
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_tes_prog_key key = {
+ KEY_INIT(devinfo->gen),
+ // XXX: not ideal, need TCS output/TES input unification
+ .inputs_read = info->inputs_read,
+ .patch_inputs_read = info->patch_inputs_read,
+ };
+
+ iris_compile_tes(ice, ish, &key);
+ }
+
+ return ish;
+}
+
+static void *
+iris_create_gs_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct iris_context *ice = (void *) ctx;
+ struct iris_screen *screen = (void *) ctx->screen;
+ struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
+
+ // XXX: NOS?
+
+ if (screen->precompile) {
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_gs_prog_key key = { KEY_INIT(devinfo->gen) };
+
+ iris_compile_gs(ice, ish, &key);
+ }
+
+ return ish;
+}
+
+static void *
+iris_create_fs_state(struct pipe_context *ctx,
+ const struct pipe_shader_state *state)
+{
+ struct iris_context *ice = (void *) ctx;
+ struct iris_screen *screen = (void *) ctx->screen;
+ struct iris_uncompiled_shader *ish = iris_create_shader_state(ctx, state);
+ struct shader_info *info = &ish->nir->info;
+
+ ish->nos |= (1ull << IRIS_NOS_FRAMEBUFFER) |
+ (1ull << IRIS_NOS_DEPTH_STENCIL_ALPHA) |
+ (1ull << IRIS_NOS_RASTERIZER) |
+ (1ull << IRIS_NOS_BLEND);
+
+ /* The program key needs the VUE map if there are > 16 inputs */
+ if (util_bitcount64(ish->nir->info.inputs_read &
+ BRW_FS_VARYING_INPUT_MASK) > 16) {
+ ish->nos |= (1ull << IRIS_NOS_LAST_VUE_MAP);
+ }
+
+ if (screen->precompile) {
+ const uint64_t color_outputs = info->outputs_written &
+ ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH) |
+ BITFIELD64_BIT(FRAG_RESULT_STENCIL) |
+ BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK));
+
+ bool can_rearrange_varyings =
+ util_bitcount64(info->inputs_read & BRW_FS_VARYING_INPUT_MASK) <= 16;
+
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_wm_prog_key key = {
+ KEY_INIT(devinfo->gen),
+ .nr_color_regions = util_bitcount(color_outputs),
+ .coherent_fb_fetch = true,
+ .input_slots_valid =
+ can_rearrange_varyings ? 0 : info->inputs_read | VARYING_BIT_POS,
+ };
+
+ iris_compile_fs(ice, ish, &key, NULL);
+ }
+
+ return ish;
+}
+
+static void *
+iris_create_compute_state(struct pipe_context *ctx,
+ const struct pipe_compute_state *state)
+{
+ assert(state->ir_type == PIPE_SHADER_IR_NIR);
+
+ struct iris_context *ice = (void *) ctx;
+ struct iris_screen *screen = (void *) ctx->screen;
+ struct iris_uncompiled_shader *ish =
+ iris_create_uncompiled_shader(ctx, (void *) state->prog, NULL);
+
+ // XXX: disallow more than 64KB of shared variables
+
+ if (screen->precompile) {
+ const struct gen_device_info *devinfo = &screen->devinfo;
+ struct brw_cs_prog_key key = { KEY_INIT(devinfo->gen) };
+
+ iris_compile_cs(ice, ish, &key);
+ }
+
+ return ish;
+}
+
+/**
+ * The pipe->delete_[stage]_state() driver hooks.
+ *
+ * Frees the iris_uncompiled_shader.
+ */
+static void
+iris_delete_shader_state(struct pipe_context *ctx, void *state)
+{
+ struct iris_uncompiled_shader *ish = state;
+
+ ralloc_free(ish->nir);
+ free(ish);
+}
+
+/**
+ * The pipe->bind_[stage]_state() driver hook.
+ *
+ * Binds an uncompiled shader as the current one for a particular stage.
+ * Updates dirty tracking to account for the shader's NOS.
+ */
+static void
+bind_state(struct iris_context *ice,
+ struct iris_uncompiled_shader *ish,
+ gl_shader_stage stage)
+{
+ uint64_t dirty_bit = IRIS_DIRTY_UNCOMPILED_VS << stage;
+ const uint64_t nos = ish ? ish->nos : 0;
+
+ const struct shader_info *old_info = iris_get_shader_info(ice, stage);
+ const struct shader_info *new_info = ish ? &ish->nir->info : NULL;
+
+ if ((old_info ? util_last_bit(old_info->textures_used) : 0) !=
+ (new_info ? util_last_bit(new_info->textures_used) : 0)) {
+ ice->state.dirty |= IRIS_DIRTY_SAMPLER_STATES_VS << stage;
+ }
+
+ ice->shaders.uncompiled[stage] = ish;
+ ice->state.dirty |= dirty_bit;
+
+ /* Record that CSOs need to mark IRIS_DIRTY_UNCOMPILED_XS when they change
+ * (or that they no longer need to do so).
+ */
+ for (int i = 0; i < IRIS_NOS_COUNT; i++) {
+ if (nos & (1 << i))
+ ice->state.dirty_for_nos[i] |= dirty_bit;
+ else
+ ice->state.dirty_for_nos[i] &= ~dirty_bit;
+ }
+}
+
+static void
+iris_bind_vs_state(struct pipe_context *ctx, void *state)
+{
+ bind_state((void *) ctx, state, MESA_SHADER_VERTEX);
+}
+
+static void
+iris_bind_tcs_state(struct pipe_context *ctx, void *state)
+{
+ bind_state((void *) ctx, state, MESA_SHADER_TESS_CTRL);
+}
+
+static void
+iris_bind_tes_state(struct pipe_context *ctx, void *state)
+{
+ struct iris_context *ice = (struct iris_context *)ctx;
+
+ /* Enabling/disabling optional stages requires a URB reconfiguration. */
+ if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
+ ice->state.dirty |= IRIS_DIRTY_URB;
+
+ bind_state((void *) ctx, state, MESA_SHADER_TESS_EVAL);
+}
+
+static void
+iris_bind_gs_state(struct pipe_context *ctx, void *state)
+{
+ struct iris_context *ice = (struct iris_context *)ctx;
+
+ /* Enabling/disabling optional stages requires a URB reconfiguration. */
+ if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY])
+ ice->state.dirty |= IRIS_DIRTY_URB;
+
+ bind_state((void *) ctx, state, MESA_SHADER_GEOMETRY);
+}
+
+static void
+iris_bind_fs_state(struct pipe_context *ctx, void *state)
+{
+ struct iris_context *ice = (struct iris_context *) ctx;
+ struct iris_uncompiled_shader *old_ish =
+ ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
+ struct iris_uncompiled_shader *new_ish = state;
+
+ const unsigned color_bits =
+ BITFIELD64_BIT(FRAG_RESULT_COLOR) |
+ BITFIELD64_RANGE(FRAG_RESULT_DATA0, BRW_MAX_DRAW_BUFFERS);
+
+ /* Fragment shader outputs influence HasWriteableRT */
+ if (!old_ish || !new_ish ||
+ (old_ish->nir->info.outputs_written & color_bits) !=
+ (new_ish->nir->info.outputs_written & color_bits))
+ ice->state.dirty |= IRIS_DIRTY_PS_BLEND;
+
+ bind_state((void *) ctx, state, MESA_SHADER_FRAGMENT);
+}
+
+static void
+iris_bind_cs_state(struct pipe_context *ctx, void *state)
+{
+ bind_state((void *) ctx, state, MESA_SHADER_COMPUTE);
}
void
projects / mesa.git / blobdiff