iris: Fix TES gl_PatchVerticesIn handling.
authorKenneth Graunke <kenneth@whitecape.org>
Fri, 8 Mar 2019 04:14:59 +0000 (20:14 -0800)
committerKenneth Graunke <kenneth@whitecape.org>
Mon, 11 Mar 2019 21:07:16 +0000 (14:07 -0700)
1. If we switch the TCS for one with a different number of output
   vertices, then the TES's gl_PatchVerticesIn value will change.
   We need to re-upload in this case.  For now, re-emit constants
   whenever the TCS/TES are swapped out.

2. If there is no TCS, then we can't grab gl_PatchVerticesIn from
   the TCS info.  Since it's a passthrough, we can just use the
   primitive's patch count (like the TCS gl_PatchVerticesIn does).

Fixes KHR-GL45.tessellation_shader.single.max_patch_vertices and
KHR-GL45.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
src/gallium/drivers/iris/iris_program.c
src/gallium/drivers/iris/iris_state.c

index 279dbc3a9436b348ee3ee32a360eadf8dbd67e55..6dc3289f6cdfbcf31a32f7e5ef67a54244a580c7 100644 (file)
@@ -912,6 +912,13 @@ iris_update_compiled_tes(struct iris_context *ice)
                           IRIS_DIRTY_BINDINGS_TES |
                           IRIS_DIRTY_CONSTANTS_TES;
    }
+
+   /* TODO: Could compare and avoid flagging this. */
+   const struct shader_info *tes_info = &ish->nir->info;
+   if (tes_info->system_values_read & (1ull << SYSTEM_VALUE_VERTICES_IN)) {
+      ice->state.dirty |= IRIS_DIRTY_CONSTANTS_TES;
+      ice->state.shaders[MESA_SHADER_TESS_EVAL].cbuf0_needs_upload = true;
+   }
 }
 
 /**
index 427419acfb916572d1f3e8ea79d68ef5dd9c87e2..d00186d66576bd8c975f633f977b7fdc658f4b78 100644 (file)
@@ -2490,9 +2490,10 @@ upload_uniforms(struct iris_context *ice,
             assert(stage == MESA_SHADER_TESS_EVAL);
             const struct shader_info *tcs_info =
                iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL);
-            assert(tcs_info);
-
-            value = tcs_info->tess.tcs_vertices_out;
+            if (tcs_info)
+               value = tcs_info->tess.tcs_vertices_out;
+            else
+               value = ice->state.vertices_per_patch;
          }
       } else if (sysval >= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X &&
                  sysval <= BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_W) {