iris: Let blorp update the clear color for us.

[mesa.git] / src / gallium / drivers / iris / iris_resource.h

diff --git a/src/gallium/drivers/iris/iris_resource.h b/src/gallium/drivers/iris/iris_resource.h
index c31f70ba058ecab3696e8a9c1be38107f4bf3ab1..19c8c87c61eac3198f5d8006880c37731fef31d4 100644 (file)
--- a/src/gallium/drivers/iris/iris_resource.h
+++ b/src/gallium/drivers/iris/iris_resource.h
@@ -86,6 +86,18 @@ struct iris_resource {
       /** Offset into 'bo' where the auxiliary surface starts. */
       uint32_t offset;
 
+      /**
+       * Fast clear color for this surface.  For depth surfaces, the clear
+       * value is stored as a float32 in the red component.
+       */
+      union isl_color_value clear_color;
+
+      /** Buffer object containing the indirect clear color.  */
+      struct iris_bo *clear_color_bo;
+
+      /** Offset into bo where the clear color can be found.  */
+      uint64_t clear_color_offset;
+
       /**
        * \brief The type of auxiliary compression used by this resource.
        *
@@ -111,7 +123,19 @@ struct iris_resource {
        * aux state for each slice.
        */
       enum isl_aux_state **state;
+
+      /**
+       * If (1 << level) is set, HiZ is enabled for that miplevel.
+       */
+      uint16_t has_hiz;
    } aux;
+
+   /**
+    * For external surfaces, this is DRM format modifier that was used to
+    * create or import the surface.  For internal surfaces, this will always
+    * be DRM_FORMAT_MOD_INVALID.
+    */
+   const struct isl_drm_modifier_info *mod_info;
 };
 
 /**
@@ -135,6 +159,8 @@ struct iris_sampler_view {
    struct pipe_sampler_view base;
    struct isl_view view;
 
+   union isl_color_value clear_color;
+
    /* A short-cut (not a reference) to the actual resource being viewed.
     * Multi-planar (or depth+stencil) images may have multiple resources
     * chained together; this skips having to traverse base->texture->*.
@@ -154,6 +180,7 @@ struct iris_sampler_view {
 struct iris_surface {
    struct pipe_surface base;
    struct isl_view view;
+   union isl_color_value clear_color;
 
    /** The resource (BO) holding our SURFACE_STATE. */
    struct iris_state_ref surface_state;
@@ -168,6 +195,11 @@ struct iris_transfer {
    void *buffer;
    void *ptr;
 
+   /** A linear staging resource for GPU-based copy_region transfers. */
+   struct pipe_resource *staging;
+   struct blorp_context *blorp;
+   struct iris_batch *batch;
+
    void (*unmap)(struct iris_transfer *);
 };
 
@@ -190,6 +222,13 @@ struct pipe_resource *iris_resource_get_separate_stencil(struct pipe_resource *)
 void iris_get_depth_stencil_resources(struct pipe_resource *res,
                                       struct iris_resource **out_z,
                                       struct iris_resource **out_s);
+bool iris_resource_set_clear_color(struct iris_context *ice,
+                                   struct iris_resource *res,
+                                   union isl_color_value color);
+union isl_color_value
+iris_resource_get_clear_color(const struct iris_resource *res,
+                              struct iris_bo **clear_color_bo,
+                              uint64_t *clear_color_offset);
 
 void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
 
@@ -205,6 +244,14 @@ void iris_resource_disable_aux(struct iris_resource *res);
 #define INTEL_REMAINING_LAYERS UINT32_MAX
 #define INTEL_REMAINING_LEVELS UINT32_MAX
 
+void
+iris_hiz_exec(struct iris_context *ice,
+              struct iris_batch *batch,
+              struct iris_resource *res,
+              unsigned int level, unsigned int start_layer,
+              unsigned int num_layers, enum isl_aux_op op,
+              bool update_clear_depth);
+
 /**
  * Prepare a miptree for access
  *
@@ -282,7 +329,8 @@ iris_resource_get_aux_state(const struct iris_resource *res,
  * use iris_resource_prepare_access or iris_resource_finish_write.
  */
 void
-iris_resource_set_aux_state(struct iris_resource *res, uint32_t level,
+iris_resource_set_aux_state(struct iris_context *ice,
+                            struct iris_resource *res, uint32_t level,
                             uint32_t start_layer, uint32_t num_layers,
                             enum isl_aux_state aux_state);
 
@@ -298,12 +346,15 @@ iris_resource_access_raw(struct iris_context *ice,
                          struct iris_batch *batch,
                          struct iris_resource *res,
                          uint32_t level, uint32_t layer,
+                         uint32_t num_layers,
                          bool write)
 {
-   iris_resource_prepare_access(ice, batch, res, level, 1, layer, 1,
+   iris_resource_prepare_access(ice, batch, res, level, 1, layer, num_layers,
                                 ISL_AUX_USAGE_NONE, false);
-   if (write)
-      iris_resource_finish_write(ice, res, level, layer, 1, ISL_AUX_USAGE_NONE);
+   if (write) {
+      iris_resource_finish_write(ice, res, level, layer, num_layers,
+                                 ISL_AUX_USAGE_NONE);
+   }
 }
 
 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,