gallium: add PIPE_CAP_TGSI_VOTE for when the VOTE ops are allowed

[mesa.git] / src / gallium / drivers / r600 / r600_pipe.c

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 27313c53f6619f75334e03243423bbce84469544..a49b00f789125f44fcc475abccacafcc929e936a 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -43,9 +43,6 @@
 
 static const struct debug_named_value r600_debug_options[] = {
        /* features */
-#if defined(R600_USE_LLVM)
-       { "llvm", DBG_LLVM, "Enable the LLVM shader compiler" },
-#endif
        { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
 
        /* shader backend */
@@ -136,7 +133,6 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen,
                goto fail;
 
        rctx->screen = rscreen;
-       rctx->keep_tiling_flags = rscreen->b.info.drm_minor >= 12;
 
        r600_init_blit_functions(rctx);
 
@@ -188,12 +184,10 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen,
        }
 
        rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
-                                      r600_context_gfx_flush, rctx,
-                                      rscreen->b.trace_bo ?
-                                              rscreen->b.trace_bo->buf : NULL);
+                                      r600_context_gfx_flush, rctx);
        rctx->b.gfx.flush = r600_context_gfx_flush;
 
-       rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024, 256,
+       rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024,
                                                             0, PIPE_USAGE_DEFAULT, FALSE);
        if (!rctx->allocator_fetch_shader)
                goto fail;
@@ -270,7 +264,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_START_INSTANCE:
        case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
        case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
-        case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+       case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
        case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
        case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
@@ -285,6 +279,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_TGSI_TXQS:
        case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
        case PIPE_CAP_INVALIDATE_BUFFER:
+       case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
+       case PIPE_CAP_QUERY_MEMORY_INFO:
+       case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
                return 1;
 
        case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
@@ -367,7 +364,11 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
        case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
        case PIPE_CAP_GENERATE_MIPMAP:
        case PIPE_CAP_STRING_MARKER:
-       case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
+       case PIPE_CAP_QUERY_BUFFER_OBJECT:
+       case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+       case PIPE_CAP_CULL_DISTANCE:
+       case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
+       case PIPE_CAP_TGSI_VOTE:
                return 0;
 
        case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
@@ -407,7 +408,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return 12;
        case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
                /* textures support 8192, but layered rendering supports 2048 */
-               return rscreen->b.info.drm_minor >= 9 ? 2048 : 0;
+               return 2048;
 
        /* Render targets. */
        case PIPE_CAP_MAX_RENDER_TARGETS:
@@ -419,10 +420,10 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 
        /* Timer queries, present when the clock frequency is non zero. */
        case PIPE_CAP_QUERY_TIME_ELAPSED:
-               return rscreen->b.info.r600_clock_crystal_freq != 0;
+               return rscreen->b.info.clock_crystal_freq != 0;
        case PIPE_CAP_QUERY_TIMESTAMP:
                return rscreen->b.info.drm_minor >= 20 &&
-                      rscreen->b.info.r600_clock_crystal_freq != 0;
+                      rscreen->b.info.clock_crystal_freq != 0;
 
        case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
        case PIPE_CAP_MIN_TEXEL_OFFSET:
@@ -438,7 +439,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return PIPE_ENDIAN_LITTLE;
 
        case PIPE_CAP_VENDOR_ID:
-               return 0x1002;
+               return ATI_VENDOR_ID;
        case PIPE_CAP_DEVICE_ID:
                return rscreen->b.info.pci_id;
        case PIPE_CAP_ACCELERATED:
@@ -449,6 +450,14 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return 0;
        case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
                return rscreen->b.chip_class >= R700;
+       case PIPE_CAP_PCI_GROUP:
+               return rscreen->b.info.pci_domain;
+       case PIPE_CAP_PCI_BUS:
+               return rscreen->b.info.pci_bus;
+       case PIPE_CAP_PCI_DEVICE:
+               return rscreen->b.info.pci_dev;
+       case PIPE_CAP_PCI_FUNCTION:
+               return rscreen->b.info.pci_func;
        }
        return 0;
 }
@@ -495,7 +504,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
        case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
                if (shader == PIPE_SHADER_COMPUTE) {
                        uint64_t max_const_buffer_size;
-                       pscreen->get_compute_param(pscreen,
+                       pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
                                PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
                                &max_const_buffer_size);
                        return max_const_buffer_size;
@@ -526,14 +535,12 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
                return 16;
         case PIPE_SHADER_CAP_PREFERRED_IR:
                if (shader == PIPE_SHADER_COMPUTE) {
-#if HAVE_LLVM < 0x0306
-                       return PIPE_SHADER_IR_LLVM;
-#else
                        return PIPE_SHADER_IR_NATIVE;
-#endif
                } else {
                        return PIPE_SHADER_IR_TGSI;
                }
+       case PIPE_SHADER_CAP_SUPPORTED_IRS:
+               return 0;
        case PIPE_SHADER_CAP_DOUBLES:
                if (rscreen->b.family == CHIP_CYPRESS ||
                        rscreen->b.family == CHIP_CAYMAN || rscreen->b.family == CHIP_ARUBA)
@@ -543,6 +550,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e
        case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
        case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
        case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
+       case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
                return 0;
        case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
                /* due to a bug in the shader compiler, some loops hang
@@ -614,8 +622,6 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
                rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
        if (!debug_get_bool_option("R600_HYPERZ", TRUE))
                rscreen->b.debug_flags |= DBG_NO_HYPERZ;
-       if (debug_get_bool_option("R600_LLVM", FALSE))
-               rscreen->b.debug_flags |= DBG_LLVM;
 
        if (rscreen->b.family == CHIP_UNKNOWN) {
                fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
@@ -704,5 +710,8 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
        }
 #endif
 
+       if (rscreen->b.debug_flags & DBG_TEST_DMA)
+               r600_test_dma(&rscreen->b);
+
        return &rscreen->b.b;
 }