SI_SGPR_BASE_VERTEX,
SI_SGPR_START_INSTANCE,
SI_SGPR_DRAWID,
- SI_ES_NUM_USER_SGPR,
-
- /* hw VS only */
- SI_SGPR_VS_STATE_BITS = SI_ES_NUM_USER_SGPR,
+ SI_SGPR_VS_STATE_BITS,
SI_VS_NUM_USER_SGPR,
- /* hw LS only */
- SI_SGPR_LS_OUT_LAYOUT = SI_ES_NUM_USER_SGPR,
- SI_LS_NUM_USER_SGPR,
-
/* both TCS and TES */
SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
SI_TES_NUM_USER_SGPR,
SI_PARAM_BASE_VERTEX,
SI_PARAM_START_INSTANCE,
SI_PARAM_DRAWID,
- /* [0] = clamp vertex color, VS as VS only */
SI_PARAM_VS_STATE_BITS,
- /* same value as TCS_IN_LAYOUT, VS as LS only */
- SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_DRAWID + 1,
- /* the other VS parameters are assigned dynamically */
/* Layout of TCS outputs in the offchip buffer
* [0:8] = the number of patches per threadgroup.
SI_PARAM_TCS_OUT_LAYOUT,
/* Layout of LS outputs / TCS inputs
- * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
- * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+ * [8:20] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
+ * [24:31] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+ * (same layout as SI_PARAM_VS_STATE_BITS)
*/
SI_PARAM_TCS_IN_LAYOUT,
/* Clamp vertex color output (only used in VS as VS). */
#define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x) & 0x1) << 0)
#define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE
+#define S_VS_STATE_INDEXED(x) (((unsigned)(x) & 0x1) << 1)
+#define C_VS_STATE_INDEXED 0xFFFFFFFD
+#define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x) & 0x1FFF) << 8)
+#define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFFE000FF
+#define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x) & 0xFF) << 24)
+#define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF
/* SI-specific system values. */
enum {
/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
unsigned type;
+ bool vs_needs_prolog;
/* GS parameters. */
unsigned esgs_itemsize;