#define SI_SHADER_H
#include <llvm-c/Core.h> /* LLVMModuleRef */
+#include <llvm-c/TargetMachine.h>
#include "tgsi/tgsi_scan.h"
+#include "util/u_queue.h"
#include "si_state.h"
-struct radeon_shader_binary;
-struct radeon_shader_reloc;
+struct ac_shader_binary;
#define SI_MAX_VS_OUTPUTS 40
-#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
-#define SI_SGPR_CONST_BUFFERS 2
-#define SI_SGPR_SAMPLERS 4 /* images & sampler states interleaved */
-/* TODO: gap */
-#define SI_SGPR_VERTEX_BUFFERS 8 /* VS only */
-#define SI_SGPR_BASE_VERTEX 10 /* VS only */
-#define SI_SGPR_START_INSTANCE 11 /* VS only */
-#define SI_SGPR_VS_STATE_BITS 12 /* VS(VS) only */
-#define SI_SGPR_LS_OUT_LAYOUT 12 /* VS(LS) only */
-#define SI_SGPR_TCS_OUT_OFFSETS 8 /* TCS & TES only */
-#define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */
-#define SI_SGPR_TCS_IN_LAYOUT 10 /* TCS only */
-#define SI_SGPR_ALPHA_REF 8 /* PS only */
-
-#define SI_VS_NUM_USER_SGPR 13 /* API VS */
-#define SI_ES_NUM_USER_SGPR 12 /* API VS */
-#define SI_LS_NUM_USER_SGPR 13 /* API VS */
-#define SI_TCS_NUM_USER_SGPR 11
-#define SI_TES_NUM_USER_SGPR 10
-#define SI_GS_NUM_USER_SGPR 8
-#define SI_GSCOPY_NUM_USER_SGPR 4
-#define SI_PS_NUM_USER_SGPR 9
+/* SGPR user data indices */
+enum {
+ SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
+ SI_SGPR_RW_BUFFERS_HI,
+ SI_SGPR_CONST_BUFFERS,
+ SI_SGPR_CONST_BUFFERS_HI,
+ SI_SGPR_SAMPLERS, /* images & sampler states interleaved */
+ SI_SGPR_SAMPLERS_HI,
+ SI_SGPR_IMAGES,
+ SI_SGPR_IMAGES_HI,
+ SI_SGPR_SHADER_BUFFERS,
+ SI_SGPR_SHADER_BUFFERS_HI,
+ SI_NUM_RESOURCE_SGPRS,
+
+ /* all VS variants */
+ SI_SGPR_VERTEX_BUFFERS = SI_NUM_RESOURCE_SGPRS,
+ SI_SGPR_VERTEX_BUFFERS_HI,
+ SI_SGPR_BASE_VERTEX,
+ SI_SGPR_START_INSTANCE,
+ SI_SGPR_DRAWID,
+ SI_SGPR_VS_STATE_BITS,
+ SI_VS_NUM_USER_SGPR,
+
+ /* both TCS and TES */
+ SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
+ SI_TES_NUM_USER_SGPR,
+
+ /* TCS only */
+ SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
+ SI_SGPR_TCS_OUT_LAYOUT,
+ SI_SGPR_TCS_IN_LAYOUT,
+ SI_TCS_NUM_USER_SGPR,
+
+ /* GS limits */
+ SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
+ SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
+
+ /* PS only */
+ SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS,
+ SI_PS_NUM_USER_SGPR,
+
+ /* CS only */
+ SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
+ SI_SGPR_BLOCK_SIZE = SI_SGPR_GRID_SIZE + 3,
+ SI_CS_NUM_USER_SGPR = SI_SGPR_BLOCK_SIZE + 3
+};
/* LLVM function parameter indices */
-#define SI_PARAM_RW_BUFFERS 0
-#define SI_PARAM_CONST_BUFFERS 1
-#define SI_PARAM_SAMPLERS 2
-#define SI_PARAM_UNUSED 3 /* TODO: use */
-
-/* VS only parameters */
-#define SI_PARAM_VERTEX_BUFFERS 4
-#define SI_PARAM_BASE_VERTEX 5
-#define SI_PARAM_START_INSTANCE 6
-/* [0] = clamp vertex color */
-#define SI_PARAM_VS_STATE_BITS 7
-/* the other VS parameters are assigned dynamically */
-
-/* Offsets where TCS outputs and TCS patch outputs live in LDS:
- * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
- * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
- */
-#define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
+enum {
+ SI_PARAM_RW_BUFFERS,
+ SI_PARAM_CONST_BUFFERS,
+ SI_PARAM_SAMPLERS,
+ SI_PARAM_IMAGES,
+ SI_PARAM_SHADER_BUFFERS,
+ SI_NUM_RESOURCE_PARAMS,
+
+ /* VS only parameters */
+ SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_BASE_VERTEX,
+ SI_PARAM_START_INSTANCE,
+ SI_PARAM_DRAWID,
+ SI_PARAM_VS_STATE_BITS,
+
+ /* Layout of TCS outputs in the offchip buffer
+ * [0:8] = the number of patches per threadgroup.
+ * [9:15] = the number of output vertices per patch.
+ * [16:31] = the offset of per patch attributes in the buffer in bytes.
+ */
+ SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
-/* Layout of TCS outputs / TES inputs:
- * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
- * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
- * [26:31] = gl_PatchVerticesIn, max = 32
- */
-#define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
+ /* TCS only parameters. */
-/* Layout of LS outputs / TCS inputs
- * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
- * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
- */
-#define SI_PARAM_TCS_IN_LAYOUT 6 /* TCS only */
-#define SI_PARAM_LS_OUT_LAYOUT 7 /* same value as TCS_IN_LAYOUT, LS only */
-
-/* TCS only parameters. */
-#define SI_PARAM_TESS_FACTOR_OFFSET 7
-#define SI_PARAM_PATCH_ID 8
-#define SI_PARAM_REL_IDS 9
-
-/* GS only parameters */
-#define SI_PARAM_GS2VS_OFFSET 4
-#define SI_PARAM_GS_WAVE_ID 5
-#define SI_PARAM_VTX0_OFFSET 6
-#define SI_PARAM_VTX1_OFFSET 7
-#define SI_PARAM_PRIMITIVE_ID 8
-#define SI_PARAM_VTX2_OFFSET 9
-#define SI_PARAM_VTX3_OFFSET 10
-#define SI_PARAM_VTX4_OFFSET 11
-#define SI_PARAM_VTX5_OFFSET 12
-#define SI_PARAM_GS_INSTANCE_ID 13
-
-/* PS only parameters */
-#define SI_PARAM_ALPHA_REF 4
-#define SI_PARAM_PRIM_MASK 5
-#define SI_PARAM_PERSP_SAMPLE 6
-#define SI_PARAM_PERSP_CENTER 7
-#define SI_PARAM_PERSP_CENTROID 8
-#define SI_PARAM_PERSP_PULL_MODEL 9
-#define SI_PARAM_LINEAR_SAMPLE 10
-#define SI_PARAM_LINEAR_CENTER 11
-#define SI_PARAM_LINEAR_CENTROID 12
-#define SI_PARAM_LINE_STIPPLE_TEX 13
-#define SI_PARAM_POS_X_FLOAT 14
-#define SI_PARAM_POS_Y_FLOAT 15
-#define SI_PARAM_POS_Z_FLOAT 16
-#define SI_PARAM_POS_W_FLOAT 17
-#define SI_PARAM_FRONT_FACE 18
-#define SI_PARAM_ANCILLARY 19
-#define SI_PARAM_SAMPLE_COVERAGE 20
-#define SI_PARAM_POS_FIXED_PT 21
-
-#define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 9) /* +8 for COLOR[0..1] */
+ /* Offsets where TCS outputs and TCS patch outputs live in LDS:
+ * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
+ * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
+ */
+ SI_PARAM_TCS_OUT_OFFSETS,
+
+ /* Layout of TCS outputs / TES inputs:
+ * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
+ * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
+ * [26:31] = gl_PatchVerticesIn, max = 32
+ */
+ SI_PARAM_TCS_OUT_LAYOUT,
+
+ /* Layout of LS outputs / TCS inputs
+ * [8:20] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
+ * [24:31] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+ * (same layout as SI_PARAM_VS_STATE_BITS)
+ */
+ SI_PARAM_TCS_IN_LAYOUT,
+
+ SI_PARAM_TCS_OC_LDS,
+ SI_PARAM_TESS_FACTOR_OFFSET,
+ SI_PARAM_PATCH_ID,
+ SI_PARAM_REL_IDS,
+
+ /* GS only parameters */
+ SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_GS_WAVE_ID,
+ SI_PARAM_VTX0_OFFSET,
+ SI_PARAM_VTX1_OFFSET,
+ SI_PARAM_PRIMITIVE_ID,
+ SI_PARAM_VTX2_OFFSET,
+ SI_PARAM_VTX3_OFFSET,
+ SI_PARAM_VTX4_OFFSET,
+ SI_PARAM_VTX5_OFFSET,
+ SI_PARAM_GS_INSTANCE_ID,
+
+ /* PS only parameters */
+ SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_PRIM_MASK,
+ SI_PARAM_PERSP_SAMPLE,
+ SI_PARAM_PERSP_CENTER,
+ SI_PARAM_PERSP_CENTROID,
+ SI_PARAM_PERSP_PULL_MODEL,
+ SI_PARAM_LINEAR_SAMPLE,
+ SI_PARAM_LINEAR_CENTER,
+ SI_PARAM_LINEAR_CENTROID,
+ SI_PARAM_LINE_STIPPLE_TEX,
+ SI_PARAM_POS_X_FLOAT,
+ SI_PARAM_POS_Y_FLOAT,
+ SI_PARAM_POS_Z_FLOAT,
+ SI_PARAM_POS_W_FLOAT,
+ SI_PARAM_FRONT_FACE,
+ SI_PARAM_ANCILLARY,
+ SI_PARAM_SAMPLE_COVERAGE,
+ SI_PARAM_POS_FIXED_PT,
+
+ /* CS only parameters */
+ SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_BLOCK_SIZE,
+ SI_PARAM_BLOCK_ID,
+ SI_PARAM_THREAD_ID,
+
+ SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
+};
+
+/* Fields of driver-defined VS state SGPR. */
+/* Clamp vertex color output (only used in VS as VS). */
+#define S_VS_STATE_CLAMP_VERTEX_COLOR(x) (((unsigned)(x) & 0x1) << 0)
+#define C_VS_STATE_CLAMP_VERTEX_COLOR 0xFFFFFFFE
+#define S_VS_STATE_INDEXED(x) (((unsigned)(x) & 0x1) << 1)
+#define C_VS_STATE_INDEXED 0xFFFFFFFD
+#define S_VS_STATE_LS_OUT_PATCH_SIZE(x) (((unsigned)(x) & 0x1FFF) << 8)
+#define C_VS_STATE_LS_OUT_PATCH_SIZE 0xFFE000FF
+#define S_VS_STATE_LS_OUT_VERTEX_SIZE(x) (((unsigned)(x) & 0xFF) << 24)
+#define C_VS_STATE_LS_OUT_VERTEX_SIZE 0x00FFFFFF
+
+/* SI-specific system values. */
+enum {
+ TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
+ TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
+};
+
+/* For VS shader key fix_fetch. */
+enum {
+ SI_FIX_FETCH_NONE = 0,
+ SI_FIX_FETCH_A2_SNORM,
+ SI_FIX_FETCH_A2_SSCALED,
+ SI_FIX_FETCH_A2_SINT,
+ SI_FIX_FETCH_RGBA_32_UNORM,
+ SI_FIX_FETCH_RGBX_32_UNORM,
+ SI_FIX_FETCH_RGBA_32_SNORM,
+ SI_FIX_FETCH_RGBX_32_SNORM,
+ SI_FIX_FETCH_RGBA_32_USCALED,
+ SI_FIX_FETCH_RGBA_32_SSCALED,
+ SI_FIX_FETCH_RGBA_32_FIXED,
+ SI_FIX_FETCH_RGBX_32_FIXED,
+ SI_FIX_FETCH_RG_64_FLOAT,
+ SI_FIX_FETCH_RGB_64_FLOAT,
+ SI_FIX_FETCH_RGBA_64_FLOAT,
+ SI_FIX_FETCH_RGB_8, /* A = 1.0 */
+ SI_FIX_FETCH_RGB_8_INT, /* A = 1 */
+ SI_FIX_FETCH_RGB_16,
+ SI_FIX_FETCH_RGB_16_INT,
+};
struct si_shader;
+/* State of the context creating the shader object. */
+struct si_compiler_ctx_state {
+ /* Should only be used by si_init_shader_selector_async and
+ * si_build_shader_variant if thread_index == -1 (non-threaded). */
+ LLVMTargetMachineRef tm;
+
+ /* Used if thread_index == -1 or if debug.async is true. */
+ struct pipe_debug_callback debug;
+
+ /* Used for creating the log string for gallium/ddebug. */
+ bool is_debug_context;
+};
+
/* A shader selector is a gallium CSO and contains shader variants and
* binaries for one TGSI program. This can be shared by multiple contexts.
*/
struct si_shader_selector {
- pipe_mutex mutex;
+ struct si_screen *screen;
+ struct util_queue_fence ready;
+ struct si_compiler_ctx_state compiler_ctx_state;
+
+ mtx_t mutex;
struct si_shader *first_variant; /* immutable after the first variant */
struct si_shader *last_variant; /* mutable */
* uploaded to a buffer).
*/
struct si_shader *main_shader_part;
+ struct si_shader *main_shader_part_ls; /* as_ls is set in the key */
+ struct si_shader *main_shader_part_es; /* as_es is set in the key */
+
+ struct si_shader *gs_copy_shader;
struct tgsi_token *tokens;
struct pipe_stream_output_info so;
/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
unsigned type;
+ bool vs_needs_prolog;
/* GS parameters. */
unsigned esgs_itemsize;
*/
unsigned colors_written_4bit;
- /* masks of "get_unique_index" bits */
- uint64_t outputs_written;
- uint32_t patch_outputs_written;
+ /* CS parameters */
+ unsigned local_size;
+
+ uint64_t outputs_written; /* "get_unique_index" bits */
+ uint32_t patch_outputs_written; /* "get_unique_index" bits */
+ uint32_t outputs_written2; /* "get_unique_index2" bits */
+
+ uint64_t inputs_read; /* "get_unique_index" bits */
+ uint32_t inputs_read2; /* "get_unique_index2" bits */
};
/* Valid shader configurations:
/* Common VS bits between the shader key and the prolog key. */
struct si_vs_prolog_bits {
- unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
+ unsigned instance_divisors[SI_MAX_ATTRIBS];
};
/* Common VS bits between the shader key and the epilog key. */
struct si_vs_epilog_bits {
unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
- /* TODO:
- * - skip clipdist, culldist (including clipvertex code) exports based
- * on which clip_plane_enable bits are set
- * - skip layer, viewport, clipdist, and culldist parameter exports
- * if PS doesn't read them
- */
};
/* Common TCS bits between the shader key and the epilog key. */
struct si_tcs_epilog_bits {
unsigned prim_mode:3;
+ unsigned tes_reads_tess_factors:1;
+};
+
+struct si_gs_prolog_bits {
+ unsigned tri_strip_adj_fix:1;
};
/* Common PS bits between the shader key and the prolog key. */
struct si_ps_prolog_bits {
unsigned color_two_side:1;
- /* TODO: add a flatshade bit that skips interpolation for colors */
+ unsigned flatshade_colors:1;
unsigned poly_stipple:1;
- unsigned force_persample_interp:1;
- /* TODO:
- * - add force_center_interp if MSAA is disabled and centroid or
- * sample are present
- * - add force_center_interp_bc_optimize to force center interpolation
- * based on the bc_optimize SGPR bit if MSAA is enabled, centroid is
- * present and sample isn't present.
- */
+ unsigned force_persp_sample_interp:1;
+ unsigned force_linear_sample_interp:1;
+ unsigned force_persp_center_interp:1;
+ unsigned force_linear_center_interp:1;
+ unsigned bc_optimize_for_persp:1;
+ unsigned bc_optimize_for_linear:1;
};
/* Common PS bits between the shader key and the epilog key. */
struct si_ps_epilog_bits {
unsigned spi_shader_col_format;
unsigned color_is_int8:8;
+ unsigned color_is_int10:8;
unsigned last_cbuf:3;
unsigned alpha_func:3;
unsigned alpha_to_one:1;
struct {
struct si_tcs_epilog_bits states;
} tcs_epilog;
+ struct {
+ struct si_gs_prolog_bits states;
+ } gs_prolog;
struct {
struct si_ps_prolog_bits states;
unsigned num_input_sgprs:5;
unsigned colors_read:8; /* color input components read */
unsigned num_interp_inputs:5; /* BCOLOR is at this location */
unsigned face_vgpr_index:5;
+ unsigned wqm:1;
char color_attr_index[2];
char color_interp_vgpr_index[2]; /* -1 == constant */
} ps_prolog;
} ps_epilog;
};
-union si_shader_key {
- struct {
- struct si_ps_prolog_bits prolog;
- struct si_ps_epilog_bits epilog;
- } ps;
- struct {
- struct si_vs_prolog_bits prolog;
- struct si_vs_epilog_bits epilog;
- unsigned as_es:1; /* export shader */
- unsigned as_ls:1; /* local shader */
- } vs;
- struct {
- struct si_tcs_epilog_bits epilog;
- } tcs; /* tessellation control shader */
- struct {
- struct si_vs_epilog_bits epilog; /* same as VS */
- unsigned as_es:1; /* export shader */
- } tes; /* tessellation evaluation shader */
+struct si_shader_key {
+ /* Prolog and epilog flags. */
+ union {
+ struct {
+ struct si_vs_prolog_bits prolog;
+ struct si_vs_epilog_bits epilog;
+ } vs;
+ struct {
+ struct si_tcs_epilog_bits epilog;
+ } tcs; /* tessellation control shader */
+ struct {
+ struct si_vs_epilog_bits epilog; /* same as VS */
+ } tes; /* tessellation evaluation shader */
+ struct {
+ struct si_gs_prolog_bits prolog;
+ } gs;
+ struct {
+ struct si_ps_prolog_bits prolog;
+ struct si_ps_epilog_bits epilog;
+ } ps;
+ } part;
+
+ /* These two are initially set according to the NEXT_SHADER property,
+ * or guessed if the property doesn't seem correct.
+ */
+ unsigned as_es:1; /* export shader, which precedes GS */
+ unsigned as_ls:1; /* local shader, which precedes TCS */
+
+ /* Flags for monolithic compilation only. */
+ union {
+ struct {
+ /* One byte for every input: SI_FIX_FETCH_* enums. */
+ uint8_t fix_fetch[SI_MAX_ATTRIBS];
+ } vs;
+ struct {
+ uint64_t inputs_to_copy; /* for fixed-func TCS */
+ } tcs;
+ } mono;
+
+ /* Optimization flags for asynchronous compilation only. */
+ union {
+ struct {
+ uint64_t kill_outputs; /* "get_unique_index" bits */
+ uint32_t kill_outputs2; /* "get_unique_index2" bits */
+ unsigned clip_disable:1;
+ } hw_vs; /* HW VS (it can be VS, TES, GS) */
+ } opt;
};
struct si_shader_config {
unsigned num_sgprs;
unsigned num_vgprs;
+ unsigned spilled_sgprs;
+ unsigned spilled_vgprs;
+ unsigned private_mem_vgprs;
unsigned lds_size;
unsigned spi_ps_input_ena;
unsigned spi_ps_input_addr;
unsigned rsrc2;
};
+enum {
+ /* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
+ EXP_PARAM_OFFSET_0 = 0,
+ EXP_PARAM_OFFSET_31 = 31,
+ /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
+ EXP_PARAM_DEFAULT_VAL_0000 = 64,
+ EXP_PARAM_DEFAULT_VAL_0001,
+ EXP_PARAM_DEFAULT_VAL_1110,
+ EXP_PARAM_DEFAULT_VAL_1111,
+ EXP_PARAM_UNDEFINED = 255,
+};
+
/* GCN-specific shader info. */
struct si_shader_info {
ubyte vs_output_param_offset[SI_MAX_VS_OUTPUTS];
};
struct si_shader {
+ struct si_compiler_ctx_state compiler_ctx_state;
+
struct si_shader_selector *selector;
struct si_shader *next_variant;
struct si_shader_part *prolog;
struct si_shader_part *epilog;
- struct si_shader *gs_copy_shader;
struct si_pm4_state *pm4;
struct r600_resource *bo;
struct r600_resource *scratch_bo;
- union si_shader_key key;
- struct radeon_shader_binary binary;
+ struct si_shader_key key;
+ struct util_queue_fence optimized_ready;
+ bool compilation_failed;
+ bool is_monolithic;
+ bool is_optimized;
bool is_binary_shared;
+ bool is_gs_copy_shader;
+
+ /* The following data is all that's needed for binary shaders. */
+ struct ac_shader_binary binary;
struct si_shader_config config;
struct si_shader_info info;
+
+ /* Shader key + LLVM IR + disassembly + statistics.
+ * Generated for debug contexts only.
+ */
+ char *shader_log;
+ size_t shader_log_size;
};
struct si_shader_part {
struct si_shader_part *next;
union si_shader_part_key key;
- struct radeon_shader_binary binary;
+ struct ac_shader_binary binary;
struct si_shader_config config;
};
-static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
-{
- if (sctx->gs_shader.cso)
- return &sctx->gs_shader.cso->info;
- else if (sctx->tes_shader.cso)
- return &sctx->tes_shader.cso->info;
- else if (sctx->vs_shader.cso)
- return &sctx->vs_shader.cso->info;
- else
- return NULL;
-}
-
-static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
-{
- if (sctx->gs_shader.current)
- return sctx->gs_shader.current->gs_copy_shader;
- else if (sctx->tes_shader.current)
- return sctx->tes_shader.current;
- else
- return sctx->vs_shader.current;
-}
-
-static inline bool si_vs_exports_prim_id(struct si_shader *shader)
-{
- if (shader->selector->type == PIPE_SHADER_VERTEX)
- return shader->key.vs.epilog.export_prim_id;
- else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
- return shader->key.tes.epilog.export_prim_id;
- else
- return false;
-}
-
/* si_shader.c */
+struct si_shader *
+si_generate_gs_copy_shader(struct si_screen *sscreen,
+ LLVMTargetMachineRef tm,
+ struct si_shader_selector *gs_selector,
+ struct pipe_debug_callback *debug);
int si_compile_tgsi_shader(struct si_screen *sscreen,
LLVMTargetMachineRef tm,
struct si_shader *shader,
int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
struct si_shader *shader,
struct pipe_debug_callback *debug);
-void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
int si_compile_llvm(struct si_screen *sscreen,
- struct radeon_shader_binary *binary,
+ struct ac_shader_binary *binary,
struct si_shader_config *conf,
LLVMTargetMachineRef tm,
LLVMModuleRef mod,
const char *name);
void si_shader_destroy(struct si_shader *shader);
unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
+unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index);
int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
- struct pipe_debug_callback *debug, unsigned processor);
+ struct pipe_debug_callback *debug, unsigned processor,
+ FILE *f, bool check_debug_option);
+void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
+ unsigned *lds_size);
void si_shader_apply_scratch_relocs(struct si_context *sctx,
struct si_shader *shader,
+ struct si_shader_config *config,
uint64_t scratch_va);
-void si_shader_binary_read_config(struct radeon_shader_binary *binary,
+void si_shader_binary_read_config(struct ac_shader_binary *binary,
struct si_shader_config *conf,
unsigned symbol_offset);
+unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
+ bool writes_samplemask);
+const char *si_get_shader_name(struct si_shader *shader, unsigned processor);
+
+/* Inline helpers. */
+
+/* Return the pointer to the main shader part's pointer. */
+static inline struct si_shader **
+si_get_main_shader_part(struct si_shader_selector *sel,
+ struct si_shader_key *key)
+{
+ if (key->as_ls)
+ return &sel->main_shader_part_ls;
+ if (key->as_es)
+ return &sel->main_shader_part_es;
+ return &sel->main_shader_part;
+}
#endif