struct radeon_shader_binary;
struct radeon_shader_reloc;
-#define SI_SGPR_RW_BUFFERS 0 /* rings (& stream-out, VS only) */
-#define SI_SGPR_CONST_BUFFERS 2
-#define SI_SGPR_SAMPLERS 4 /* images & sampler states interleaved */
-/* TODO: gap */
-#define SI_SGPR_VERTEX_BUFFERS 8 /* VS only */
-#define SI_SGPR_BASE_VERTEX 10 /* VS only */
-#define SI_SGPR_START_INSTANCE 11 /* VS only */
-#define SI_SGPR_VS_STATE_BITS 12 /* VS(VS) only */
-#define SI_SGPR_LS_OUT_LAYOUT 12 /* VS(LS) only */
-#define SI_SGPR_TCS_OUT_OFFSETS 8 /* TCS & TES only */
-#define SI_SGPR_TCS_OUT_LAYOUT 9 /* TCS & TES only */
-#define SI_SGPR_TCS_IN_LAYOUT 10 /* TCS only */
-#define SI_SGPR_ALPHA_REF 8 /* PS only */
-
-#define SI_VS_NUM_USER_SGPR 13 /* API VS */
-#define SI_ES_NUM_USER_SGPR 12 /* API VS */
-#define SI_LS_NUM_USER_SGPR 13 /* API VS */
-#define SI_TCS_NUM_USER_SGPR 11
-#define SI_TES_NUM_USER_SGPR 10
-#define SI_GS_NUM_USER_SGPR 8
-#define SI_GSCOPY_NUM_USER_SGPR 4
-#define SI_PS_NUM_USER_SGPR 9
+#define SI_MAX_VS_OUTPUTS 40
+
+/* SGPR user data indices */
+enum {
+ SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
+ SI_SGPR_RW_BUFFERS_HI,
+ SI_SGPR_CONST_BUFFERS,
+ SI_SGPR_CONST_BUFFERS_HI,
+ SI_SGPR_SAMPLERS, /* images & sampler states interleaved */
+ SI_SGPR_SAMPLERS_HI,
+ SI_SGPR_IMAGES,
+ SI_SGPR_IMAGES_HI,
+ SI_SGPR_SHADER_BUFFERS,
+ SI_SGPR_SHADER_BUFFERS_HI,
+ SI_NUM_RESOURCE_SGPRS,
+
+ /* all VS variants */
+ SI_SGPR_VERTEX_BUFFERS = SI_NUM_RESOURCE_SGPRS,
+ SI_SGPR_VERTEX_BUFFERS_HI,
+ SI_SGPR_BASE_VERTEX,
+ SI_SGPR_START_INSTANCE,
+ SI_SGPR_DRAWID,
+ SI_ES_NUM_USER_SGPR,
+
+ /* hw VS only */
+ SI_SGPR_VS_STATE_BITS = SI_ES_NUM_USER_SGPR,
+ SI_VS_NUM_USER_SGPR,
+
+ /* hw LS only */
+ SI_SGPR_LS_OUT_LAYOUT = SI_ES_NUM_USER_SGPR,
+ SI_LS_NUM_USER_SGPR,
+
+ /* both TCS and TES */
+ SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS,
+ SI_TES_NUM_USER_SGPR,
+
+ /* TCS only */
+ SI_SGPR_TCS_OUT_OFFSETS = SI_TES_NUM_USER_SGPR,
+ SI_SGPR_TCS_OUT_LAYOUT,
+ SI_SGPR_TCS_IN_LAYOUT,
+ SI_TCS_NUM_USER_SGPR,
+
+ /* GS limits */
+ SI_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
+ SI_GSCOPY_NUM_USER_SGPR = SI_SGPR_RW_BUFFERS_HI + 1,
+
+ /* PS only */
+ SI_SGPR_ALPHA_REF = SI_NUM_RESOURCE_SGPRS,
+ SI_PS_NUM_USER_SGPR,
+
+ /* CS only */
+ SI_SGPR_GRID_SIZE = SI_NUM_RESOURCE_SGPRS,
+ SI_CS_NUM_USER_SGPR = SI_SGPR_GRID_SIZE + 3
+};
/* LLVM function parameter indices */
-#define SI_PARAM_RW_BUFFERS 0
-#define SI_PARAM_CONST_BUFFERS 1
-#define SI_PARAM_SAMPLERS 2
-#define SI_PARAM_UNUSED 3 /* TODO: use */
-
-/* VS only parameters */
-#define SI_PARAM_VERTEX_BUFFERS 4
-#define SI_PARAM_BASE_VERTEX 5
-#define SI_PARAM_START_INSTANCE 6
-/* [0] = clamp vertex color */
-#define SI_PARAM_VS_STATE_BITS 7
-/* the other VS parameters are assigned dynamically */
-
-/* Offsets where TCS outputs and TCS patch outputs live in LDS:
- * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
- * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
- */
-#define SI_PARAM_TCS_OUT_OFFSETS 4 /* for TCS & TES */
+enum {
+ SI_PARAM_RW_BUFFERS,
+ SI_PARAM_CONST_BUFFERS,
+ SI_PARAM_SAMPLERS,
+ SI_PARAM_IMAGES,
+ SI_PARAM_SHADER_BUFFERS,
+ SI_NUM_RESOURCE_PARAMS,
+
+ /* VS only parameters */
+ SI_PARAM_VERTEX_BUFFERS = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_BASE_VERTEX,
+ SI_PARAM_START_INSTANCE,
+ SI_PARAM_DRAWID,
+ /* [0] = clamp vertex color, VS as VS only */
+ SI_PARAM_VS_STATE_BITS,
+ /* same value as TCS_IN_LAYOUT, VS as LS only */
+ SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_DRAWID + 1,
+ /* the other VS parameters are assigned dynamically */
+
+ /* Layout of TCS outputs in the offchip buffer
+ * [0:8] = the number of patches per threadgroup.
+ * [9:15] = the number of output vertices per patch.
+ * [16:31] = the offset of per patch attributes in the buffer in bytes.
+ */
+ SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */
-/* Layout of TCS outputs / TES inputs:
- * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
- * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
- * [26:31] = gl_PatchVerticesIn, max = 32
- */
-#define SI_PARAM_TCS_OUT_LAYOUT 5 /* for TCS & TES */
+ /* TCS only parameters. */
-/* Layout of LS outputs / TCS inputs
- * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
- * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
- */
-#define SI_PARAM_TCS_IN_LAYOUT 6 /* TCS only */
-#define SI_PARAM_LS_OUT_LAYOUT 7 /* same value as TCS_IN_LAYOUT, LS only */
-
-/* TCS only parameters. */
-#define SI_PARAM_TESS_FACTOR_OFFSET 7
-#define SI_PARAM_PATCH_ID 8
-#define SI_PARAM_REL_IDS 9
-
-/* GS only parameters */
-#define SI_PARAM_GS2VS_OFFSET 4
-#define SI_PARAM_GS_WAVE_ID 5
-#define SI_PARAM_VTX0_OFFSET 6
-#define SI_PARAM_VTX1_OFFSET 7
-#define SI_PARAM_PRIMITIVE_ID 8
-#define SI_PARAM_VTX2_OFFSET 9
-#define SI_PARAM_VTX3_OFFSET 10
-#define SI_PARAM_VTX4_OFFSET 11
-#define SI_PARAM_VTX5_OFFSET 12
-#define SI_PARAM_GS_INSTANCE_ID 13
-
-/* PS only parameters */
-#define SI_PARAM_ALPHA_REF 4
-#define SI_PARAM_PRIM_MASK 5
-#define SI_PARAM_PERSP_SAMPLE 6
-#define SI_PARAM_PERSP_CENTER 7
-#define SI_PARAM_PERSP_CENTROID 8
-#define SI_PARAM_PERSP_PULL_MODEL 9
-#define SI_PARAM_LINEAR_SAMPLE 10
-#define SI_PARAM_LINEAR_CENTER 11
-#define SI_PARAM_LINEAR_CENTROID 12
-#define SI_PARAM_LINE_STIPPLE_TEX 13
-#define SI_PARAM_POS_X_FLOAT 14
-#define SI_PARAM_POS_Y_FLOAT 15
-#define SI_PARAM_POS_Z_FLOAT 16
-#define SI_PARAM_POS_W_FLOAT 17
-#define SI_PARAM_FRONT_FACE 18
-#define SI_PARAM_ANCILLARY 19
-#define SI_PARAM_SAMPLE_COVERAGE 20
-#define SI_PARAM_POS_FIXED_PT 21
-
-#define SI_NUM_PARAMS (SI_PARAM_POS_FIXED_PT + 1)
+ /* Offsets where TCS outputs and TCS patch outputs live in LDS:
+ * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32
+ * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32
+ */
+ SI_PARAM_TCS_OUT_OFFSETS,
+
+ /* Layout of TCS outputs / TES inputs:
+ * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4
+ * [13:20] = stride between output vertices in dwords = num_inputs * 4, max = 32*4
+ * [26:31] = gl_PatchVerticesIn, max = 32
+ */
+ SI_PARAM_TCS_OUT_LAYOUT,
+
+ /* Layout of LS outputs / TCS inputs
+ * [0:12] = stride between patches in dwords = num_inputs * num_vertices * 4, max = 32*32*4
+ * [13:20] = stride between vertices in dwords = num_inputs * 4, max = 32*4
+ */
+ SI_PARAM_TCS_IN_LAYOUT,
+
+ SI_PARAM_TCS_OC_LDS,
+ SI_PARAM_TESS_FACTOR_OFFSET,
+ SI_PARAM_PATCH_ID,
+ SI_PARAM_REL_IDS,
+
+ /* GS only parameters */
+ SI_PARAM_GS2VS_OFFSET = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_GS_WAVE_ID,
+ SI_PARAM_VTX0_OFFSET,
+ SI_PARAM_VTX1_OFFSET,
+ SI_PARAM_PRIMITIVE_ID,
+ SI_PARAM_VTX2_OFFSET,
+ SI_PARAM_VTX3_OFFSET,
+ SI_PARAM_VTX4_OFFSET,
+ SI_PARAM_VTX5_OFFSET,
+ SI_PARAM_GS_INSTANCE_ID,
+
+ /* PS only parameters */
+ SI_PARAM_ALPHA_REF = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_PRIM_MASK,
+ SI_PARAM_PERSP_SAMPLE,
+ SI_PARAM_PERSP_CENTER,
+ SI_PARAM_PERSP_CENTROID,
+ SI_PARAM_PERSP_PULL_MODEL,
+ SI_PARAM_LINEAR_SAMPLE,
+ SI_PARAM_LINEAR_CENTER,
+ SI_PARAM_LINEAR_CENTROID,
+ SI_PARAM_LINE_STIPPLE_TEX,
+ SI_PARAM_POS_X_FLOAT,
+ SI_PARAM_POS_Y_FLOAT,
+ SI_PARAM_POS_Z_FLOAT,
+ SI_PARAM_POS_W_FLOAT,
+ SI_PARAM_FRONT_FACE,
+ SI_PARAM_ANCILLARY,
+ SI_PARAM_SAMPLE_COVERAGE,
+ SI_PARAM_POS_FIXED_PT,
+
+ /* CS only parameters */
+ SI_PARAM_GRID_SIZE = SI_NUM_RESOURCE_PARAMS,
+ SI_PARAM_BLOCK_ID,
+ SI_PARAM_THREAD_ID,
+
+ SI_NUM_PARAMS = SI_PARAM_POS_FIXED_PT + 9, /* +8 for COLOR[0..1] */
+};
+
+/* SI-specific system values. */
+enum {
+ TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
+ TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
+};
struct si_shader;
* binaries for one TGSI program. This can be shared by multiple contexts.
*/
struct si_shader_selector {
+ struct si_screen *screen;
+ struct util_queue_fence ready;
+
+ /* Should only be used by si_init_shader_selector_async
+ * if thread_index == -1 (non-threaded). */
+ LLVMTargetMachineRef tm;
+ struct pipe_debug_callback debug;
+ bool is_debug_context;
+
pipe_mutex mutex;
struct si_shader *first_variant; /* immutable after the first variant */
struct si_shader *last_variant; /* mutable */
+ /* The compiled TGSI shader expecting a prolog and/or epilog (not
+ * uploaded to a buffer).
+ */
+ struct si_shader *main_shader_part;
+
struct tgsi_token *tokens;
struct pipe_stream_output_info so;
struct tgsi_shader_info info;
unsigned max_gsvs_emit_size;
/* PS parameters. */
+ unsigned color_attr_index[2];
unsigned db_shader_control;
/* Set 0xf or 0x0 (4 bits) per each written output.
* ANDed with spi_shader_col_format.
*/
unsigned colors_written_4bit;
+ /* CS parameters */
+ unsigned local_size;
+
/* masks of "get_unique_index" bits */
uint64_t outputs_written;
uint32_t patch_outputs_written;
* With both: LS | HS | ES | GS | VS | PS
*/
+/* Common VS bits between the shader key and the prolog key. */
+struct si_vs_prolog_bits {
+ unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
+};
+
+/* Common VS bits between the shader key and the epilog key. */
+struct si_vs_epilog_bits {
+ unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
+ /* TODO:
+ * - skip clipdist, culldist (including clipvertex code) exports based
+ * on which clip_plane_enable bits are set
+ * - skip layer, viewport, clipdist, and culldist parameter exports
+ * if PS doesn't read them
+ */
+};
+
+/* Common TCS bits between the shader key and the epilog key. */
+struct si_tcs_epilog_bits {
+ unsigned prim_mode:3;
+ uint64_t inputs_to_copy;
+};
+
+/* Common PS bits between the shader key and the prolog key. */
+struct si_ps_prolog_bits {
+ unsigned color_two_side:1;
+ unsigned flatshade_colors:1;
+ unsigned poly_stipple:1;
+ unsigned force_persp_sample_interp:1;
+ unsigned force_linear_sample_interp:1;
+ unsigned force_persp_center_interp:1;
+ unsigned force_linear_center_interp:1;
+ unsigned bc_optimize_for_persp:1;
+ unsigned bc_optimize_for_linear:1;
+};
+
+/* Common PS bits between the shader key and the epilog key. */
+struct si_ps_epilog_bits {
+ unsigned spi_shader_col_format;
+ unsigned color_is_int8:8;
+ unsigned last_cbuf:3;
+ unsigned alpha_func:3;
+ unsigned alpha_to_one:1;
+ unsigned poly_line_smoothing:1;
+ unsigned clamp_color:1;
+};
+
+union si_shader_part_key {
+ struct {
+ struct si_vs_prolog_bits states;
+ unsigned num_input_sgprs:5;
+ unsigned last_input:4;
+ } vs_prolog;
+ struct {
+ struct si_vs_epilog_bits states;
+ unsigned prim_id_param_offset:5;
+ } vs_epilog;
+ struct {
+ struct si_tcs_epilog_bits states;
+ } tcs_epilog;
+ struct {
+ struct si_ps_prolog_bits states;
+ unsigned num_input_sgprs:5;
+ unsigned num_input_vgprs:5;
+ /* Color interpolation and two-side color selection. */
+ unsigned colors_read:8; /* color input components read */
+ unsigned num_interp_inputs:5; /* BCOLOR is at this location */
+ unsigned face_vgpr_index:5;
+ unsigned wqm:1;
+ char color_attr_index[2];
+ char color_interp_vgpr_index[2]; /* -1 == constant */
+ } ps_prolog;
+ struct {
+ struct si_ps_epilog_bits states;
+ unsigned colors_written:8;
+ unsigned writes_z:1;
+ unsigned writes_stencil:1;
+ unsigned writes_samplemask:1;
+ } ps_epilog;
+};
+
union si_shader_key {
struct {
- unsigned spi_shader_col_format;
- unsigned color_is_int8:8;
- unsigned last_cbuf:3;
- unsigned color_two_side:1;
- unsigned alpha_func:3;
- unsigned alpha_to_one:1;
- unsigned poly_stipple:1;
- unsigned poly_line_smoothing:1;
- unsigned clamp_color:1;
- unsigned force_persample_interp:1;
+ struct si_ps_prolog_bits prolog;
+ struct si_ps_epilog_bits epilog;
} ps;
struct {
- unsigned instance_divisors[SI_NUM_VERTEX_BUFFERS];
- /* Mask of "get_unique_index" bits - which outputs are read
- * by the next stage (needed by ES).
- * This describes how outputs are laid out in memory. */
+ struct si_vs_prolog_bits prolog;
+ struct si_vs_epilog_bits epilog;
unsigned as_es:1; /* export shader */
unsigned as_ls:1; /* local shader */
- unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
} vs;
struct {
- unsigned prim_mode:3;
+ struct si_tcs_epilog_bits epilog;
} tcs; /* tessellation control shader */
struct {
- /* Mask of "get_unique_index" bits - which outputs are read
- * by the next stage (needed by ES).
- * This describes how outputs are laid out in memory. */
+ struct si_vs_epilog_bits epilog; /* same as VS */
unsigned as_es:1; /* export shader */
- unsigned export_prim_id:1; /* when PS needs it and GS is disabled */
} tes; /* tessellation evaluation shader */
};
struct si_shader_config {
unsigned num_sgprs;
unsigned num_vgprs;
+ unsigned spilled_sgprs;
+ unsigned spilled_vgprs;
unsigned lds_size;
unsigned spi_ps_input_ena;
unsigned spi_ps_input_addr;
unsigned rsrc2;
};
+/* GCN-specific shader info. */
+struct si_shader_info {
+ ubyte vs_output_param_offset[SI_MAX_VS_OUTPUTS];
+ ubyte num_input_sgprs;
+ ubyte num_input_vgprs;
+ char face_vgpr_index;
+ bool uses_instanceid;
+ ubyte nr_pos_exports;
+ ubyte nr_param_exports;
+};
+
struct si_shader {
struct si_shader_selector *selector;
struct si_shader *next_variant;
+ struct si_shader_part *prolog;
+ struct si_shader_part *epilog;
+
struct si_shader *gs_copy_shader;
struct si_pm4_state *pm4;
struct r600_resource *bo;
struct r600_resource *scratch_bo;
union si_shader_key key;
+ bool is_binary_shared;
+ unsigned z_order;
+
+ /* The following data is all that's needed for binary shaders. */
struct radeon_shader_binary binary;
struct si_shader_config config;
+ struct si_shader_info info;
- unsigned vs_output_param_offset[PIPE_MAX_SHADER_OUTPUTS];
- bool uses_instanceid;
- unsigned nr_pos_exports;
- unsigned nr_param_exports;
+ /* Shader key + LLVM IR + disassembly + statistics.
+ * Generated for debug contexts only.
+ */
+ char *shader_log;
+ size_t shader_log_size;
+};
+
+struct si_shader_part {
+ struct si_shader_part *next;
+ union si_shader_part_key key;
+ struct radeon_shader_binary binary;
+ struct si_shader_config config;
};
static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
static inline bool si_vs_exports_prim_id(struct si_shader *shader)
{
if (shader->selector->type == PIPE_SHADER_VERTEX)
- return shader->key.vs.export_prim_id;
+ return shader->key.vs.epilog.export_prim_id;
else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
- return shader->key.tes.export_prim_id;
+ return shader->key.tes.epilog.export_prim_id;
else
return false;
}
-/* radeonsi_shader.c */
+/* si_shader.c */
+int si_compile_tgsi_shader(struct si_screen *sscreen,
+ LLVMTargetMachineRef tm,
+ struct si_shader *shader,
+ bool is_monolithic,
+ struct pipe_debug_callback *debug);
int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
struct si_shader *shader,
struct pipe_debug_callback *debug);
-void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f);
int si_compile_llvm(struct si_screen *sscreen,
struct radeon_shader_binary *binary,
struct si_shader_config *conf,
unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index);
int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader);
void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
- struct pipe_debug_callback *debug, unsigned processor);
+ struct pipe_debug_callback *debug, unsigned processor,
+ FILE *f);
void si_shader_apply_scratch_relocs(struct si_context *sctx,
struct si_shader *shader,
+ struct si_shader_config *config,
uint64_t scratch_va);
void si_shader_binary_read_config(struct radeon_shader_binary *binary,
struct si_shader_config *conf,
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