#include "si_pipe.h"
#include "sid.h"
+#include "gfx9d.h"
#include "radeon/r600_cs.h"
#include "tgsi/tgsi_parse.h"
/* There is always a size of data followed by the data itself. */
unsigned relocs_size = shader->binary.reloc_count *
sizeof(shader->binary.relocs[0]);
- unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
+ unsigned disasm_size = shader->binary.disasm_string ?
+ strlen(shader->binary.disasm_string) + 1 : 0;
unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
strlen(shader->binary.llvm_ir_string) + 1 : 0;
unsigned size =
return shader->pm4;
}
-static void si_shader_ls(struct si_shader *shader)
+static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
{
struct si_pm4_state *pm4;
unsigned vgpr_comp_cnt;
uint64_t va;
+ assert(sscreen->b.chip_class <= VI);
+
pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
S_00B528_DX10_CLAMP(1) |
S_00B528_FLOAT_MODE(shader->config.float_mode);
- shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
+ shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
}
-static void si_shader_hs(struct si_shader *shader)
+static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
{
struct si_pm4_state *pm4;
uint64_t va;
S_00B428_FLOAT_MODE(shader->config.float_mode));
si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
- S_00B42C_OC_LDS_EN(1) |
+ S_00B42C_OC_LDS_EN(sscreen->b.chip_class <= VI) |
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
}
uint64_t va;
unsigned oc_lds_en;
+ assert(sscreen->b.chip_class <= VI);
+
pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
if (shader->selector->type == PIPE_SHADER_VERTEX) {
vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
- num_user_sgprs = SI_ES_NUM_USER_SGPR;
+ num_user_sgprs = SI_VS_NUM_USER_SGPR;
} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
vgpr_comp_cnt = 3; /* all components are needed for TES */
num_user_sgprs = SI_TES_NUM_USER_SGPR;
if (!pm4)
return;
- si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
-
offset = num_components[0] * sel->gs_max_out_vertices;
si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
if (max_stream >= 1)
switch (shader->selector->type) {
case PIPE_SHADER_VERTEX:
if (shader->key.as_ls)
- si_shader_ls(shader);
+ si_shader_ls(sscreen, shader);
else if (shader->key.as_es)
si_shader_es(sscreen, shader);
else
si_shader_vs(sscreen, shader, NULL);
break;
case PIPE_SHADER_TESS_CTRL:
- si_shader_hs(shader);
+ si_shader_hs(sscreen, shader);
break;
case PIPE_SHADER_TESS_EVAL:
if (shader->key.as_es)
sel->type = sel->info.processor;
p_atomic_inc(&sscreen->b.num_shaders_created);
+ /* The prolog is a no-op if there are no inputs. */
+ sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
+ sel->info.num_inputs;
+
/* Set which opcode uses which (i,j) pair. */
if (sel->info.uses_persp_opcode_interp_centroid)
sel->info.uses_persp_centroid = true;
if (shader->pm4) {
switch (shader->selector->type) {
case PIPE_SHADER_VERTEX:
- if (shader->key.as_ls)
+ if (shader->key.as_ls) {
+ assert(sctx->b.chip_class <= VI);
si_pm4_delete_state(sctx, ls, shader->pm4);
- else if (shader->key.as_es)
+ } else if (shader->key.as_es) {
+ assert(sctx->b.chip_class <= VI);
si_pm4_delete_state(sctx, es, shader->pm4);
- else
+ } else {
si_pm4_delete_state(sctx, vs, shader->pm4);
+ }
break;
case PIPE_SHADER_TESS_CTRL:
si_pm4_delete_state(sctx, hs, shader->pm4);
break;
case PIPE_SHADER_TESS_EVAL:
- if (shader->key.as_es)
+ if (shader->key.as_es) {
+ assert(sctx->b.chip_class <= VI);
si_pm4_delete_state(sctx, es, shader->pm4);
- else
+ } else {
si_pm4_delete_state(sctx, vs, shader->pm4);
+ }
break;
case PIPE_SHADER_GEOMETRY:
if (shader->is_gs_copy_shader)
/* Some rings don't have to be allocated if shaders don't use them.
* (e.g. no varyings between ES and GS or GS and VS)
+ *
+ * GFX9 doesn't have the ESGS ring.
*/
- bool update_esgs = esgs_ring_size &&
+ bool update_esgs = sctx->b.chip_class <= VI &&
+ esgs_ring_size &&
(!sctx->esgs_ring ||
sctx->esgs_ring->width0 < esgs_ring_size);
bool update_gsvs = gsvs_ring_size &&
return false;
if (sctx->b.chip_class >= CIK) {
- if (sctx->esgs_ring)
+ if (sctx->esgs_ring) {
+ assert(sctx->b.chip_class <= VI);
si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
sctx->esgs_ring->width0 / 256);
+ }
if (sctx->gsvs_ring)
si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
sctx->gsvs_ring->width0 / 256);
/* Set ring bindings. */
if (sctx->esgs_ring) {
+ assert(sctx->b.chip_class <= VI);
si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
true, true, 4, 64, 0);
max_offchip_buffers = MIN2(max_offchip_buffers, 126);
break;
case CIK:
+ case VI:
+ case GFX9:
max_offchip_buffers = MIN2(max_offchip_buffers, 508);
break;
- case VI:
default:
- max_offchip_buffers = MIN2(max_offchip_buffers, 512);
- break;
+ assert(0);
+ return;
}
assert(!sctx->tf_ring);
S_030938_SIZE(sctx->tf_ring->width0 / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
r600_resource(sctx->tf_ring)->gpu_address >> 8);
+ if (sctx->b.chip_class >= GFX9)
+ si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
+ r600_resource(sctx->tf_ring)->gpu_address >> 40);
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
}
/* VS as LS */
- r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
- if (r)
- return false;
- si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
+ if (sctx->b.chip_class <= VI) {
+ r = si_shader_select(ctx, &sctx->vs_shader,
+ &compiler_state);
+ if (r)
+ return false;
+ si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
+ }
if (sctx->tcs_shader.cso) {
r = si_shader_select(ctx, &sctx->tcs_shader,
sctx->fixed_func_tcs_shader.current->pm4);
}
- r = si_shader_select(ctx, &sctx->tes_shader, &compiler_state);
- if (r)
- return false;
-
if (sctx->gs_shader.cso) {
/* TES as ES */
- si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
+ if (sctx->b.chip_class <= VI) {
+ r = si_shader_select(ctx, &sctx->tes_shader,
+ &compiler_state);
+ if (r)
+ return false;
+ si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
+ }
} else {
/* TES as VS */
+ r = si_shader_select(ctx, &sctx->tes_shader,
+ &compiler_state);
+ if (r)
+ return false;
si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
si_update_so(sctx, sctx->tes_shader.cso);
}
} else if (sctx->gs_shader.cso) {
- /* VS as ES */
- r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
- if (r)
- return false;
- si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
+ if (sctx->b.chip_class <= VI) {
+ /* VS as ES */
+ r = si_shader_select(ctx, &sctx->vs_shader,
+ &compiler_state);
+ if (r)
+ return false;
+ si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
- si_pm4_bind_state(sctx, ls, NULL);
- si_pm4_bind_state(sctx, hs, NULL);
+ si_pm4_bind_state(sctx, ls, NULL);
+ si_pm4_bind_state(sctx, hs, NULL);
+ }
} else {
/* VS as VS */
r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
return false;
} else {
si_pm4_bind_state(sctx, gs, NULL);
- si_pm4_bind_state(sctx, es, NULL);
+ if (sctx->b.chip_class <= VI)
+ si_pm4_bind_state(sctx, es, NULL);
}
si_update_vgt_shader_config(sctx);
si_mark_atom_dirty(sctx, &sctx->spi_map);
}
- if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
+ if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
if (sctx->ps_db_shader_control != db_shader_control) {
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