i965/vec4: Lower ARB_shader_group_vote intrinsics

[mesa.git] / src / intel / compiler / brw_nir.h

diff --git a/src/intel/compiler/brw_nir.h b/src/intel/compiler/brw_nir.h
index 76d7ec89f9b896bb4d26b170ad53269145f42106..560027c3662e8c43652646e3c087c85cd8ba69c9 100644 (file)
--- a/src/intel/compiler/brw_nir.h
+++ b/src/intel/compiler/brw_nir.h
@@ -21,7 +21,8 @@
  * IN THE SOFTWARE.
  */
 
-#pragma once
+#ifndef BRW_NIR_H
+#define BRW_NIR_H
 
 #include "brw_reg.h"
 #include "compiler/nir/nir.h"
@@ -97,10 +98,9 @@ nir_shader *brw_preprocess_nir(const struct brw_compiler *compiler,
 bool brw_nir_lower_intrinsics(nir_shader *nir,
                               struct brw_stage_prog_data *prog_data);
 void brw_nir_lower_vs_inputs(nir_shader *nir,
-                             bool is_scalar,
                              bool use_legacy_snorm_formula,
                              const uint8_t *vs_attrib_wa_flags);
-void brw_nir_lower_vue_inputs(nir_shader *nir, bool is_scalar,
+void brw_nir_lower_vue_inputs(nir_shader *nir,
                               const struct brw_vue_map *vue_map);
 void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue);
 void brw_nir_lower_fs_inputs(nir_shader *nir,
@@ -142,6 +142,10 @@ void brw_nir_setup_glsl_uniforms(nir_shader *shader,
 void brw_nir_setup_arb_uniforms(nir_shader *shader, struct gl_program *prog,
                                 struct brw_stage_prog_data *stage_prog_data);
 
+void brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
+                                nir_shader *nir,
+                                struct brw_ubo_range out_ranges[4]);
+
 bool brw_nir_opt_peephole_ffma(nir_shader *shader);
 
 #define BRW_NIR_FRAG_OUTPUT_INDEX_SHIFT 0
@@ -152,3 +156,5 @@ bool brw_nir_opt_peephole_ffma(nir_shader *shader);
 #ifdef __cplusplus
 }
 #endif
+
+#endif /* BRW_NIR_H */