/* writemask */
%type <integer> writemask_x writemask_y writemask_z writemask_w
-%type <reg> writemask
+%type <integer> writemask
/* dst operand */
%type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg
%type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srcimm
%type <reg> indirectgenreg indirectregion
%type <reg> immreg src reg32 payload directgenreg_list addrparam region
-%type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
+%type <reg> region_wh directgenreg directmsgreg indirectmsgreg
+%type <integer> swizzle
/* registers */
%type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
/* Sync instruction */
syncinstruction:
- WAIT execsize src instoptions
+ WAIT execsize dst instoptions
{
brw_next_insn(p, $1);
i965_asm_set_instruction_options(p, $4);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
brw_set_default_access_mode(p, $4.access_mode);
- struct brw_reg src = brw_notification_reg();
- brw_set_dest(p, brw_last_inst, src);
- brw_set_src0(p, brw_last_inst, src);
+ struct brw_reg dest = $3;
+ dest.swizzle = brw_swizzle_for_mask(dest.writemask);
+ if (dest.file != ARF || dest.nr != BRW_ARF_NOTIFICATION_COUNT)
+ error(&@1, "WAIT must use the notification register\n");
+ brw_set_dest(p, brw_last_inst, dest);
+ brw_set_src0(p, brw_last_inst, dest);
brw_set_src1(p, brw_last_inst, brw_null_reg());
brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
}
dstreg dstregion writemask reg_type
{
$$ = $1;
-
- if ($2 == -1) {
- $$.hstride = BRW_HORIZONTAL_STRIDE_1;
- $$.vstride = BRW_VERTICAL_STRIDE_1;
- $$.width = BRW_WIDTH_1;
- } else {
- $$.hstride = $2;
- }
+ $$.vstride = BRW_VERTICAL_STRIDE_1;
+ $$.width = BRW_WIDTH_1;
+ $$.hstride = $2;
$$.type = $4;
- $$.writemask = $3.writemask;
+ $$.writemask = $3;
$$.swizzle = BRW_SWIZZLE_NOOP;
$$.subnr = $$.subnr * brw_reg_type_to_size($4);
}
$$ = $1;
$$.hstride = $2;
$$.type = $4;
- $$.writemask = $3.writemask;
+ $$.writemask = $3;
$$.subnr = $$.subnr * brw_reg_type_to_size($4);
}
/* BSpec says "When the conditional modifier is present, updates
| nullreg dstregion writemask reg_type
{
$$ = $1;
- if ($2 == -1) {
- $$.hstride = BRW_HORIZONTAL_STRIDE_1;
- $$.vstride = BRW_VERTICAL_STRIDE_1;
- $$.width = BRW_WIDTH_1;
- } else {
- $$.hstride = $2;
- }
- $$.writemask = $3.writemask;
+ $$.vstride = BRW_VERTICAL_STRIDE_1;
+ $$.width = BRW_WIDTH_1;
+ $$.hstride = $2;
+ $$.writemask = $3;
$$.type = $4;
}
| threadcontrolreg
| flagreg
| ipreg
| maskreg
+ | notifyreg
| performancereg
| statereg
;
immreg:
immval imm_type
{
- uint32_t u32;
- uint64_t u64;
switch ($2) {
case BRW_REGISTER_TYPE_UD:
- u32 = $1;
- $$ = brw_imm_ud(u32);
+ $$ = brw_imm_ud($1);
break;
case BRW_REGISTER_TYPE_D:
$$ = brw_imm_d($1);
break;
case BRW_REGISTER_TYPE_UW:
- u32 = $1 | ($1 << 16);
- $$ = brw_imm_uw(u32);
+ $$ = brw_imm_uw($1 | ($1 << 16));
break;
case BRW_REGISTER_TYPE_W:
- u32 = $1;
- $$ = brw_imm_w(u32);
+ $$ = brw_imm_w($1);
break;
case BRW_REGISTER_TYPE_F:
$$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
+ /* Set u64 instead of ud since DIM uses a 64-bit F-typed imm */
$$.u64 = $1;
- $$.ud = $1;
break;
case BRW_REGISTER_TYPE_V:
$$ = brw_imm_v($1);
$$ = brw_imm_uv($1);
break;
case BRW_REGISTER_TYPE_VF:
- $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
- $$.d = $1;
+ $$ = brw_imm_vf($1);
break;
case BRW_REGISTER_TYPE_Q:
- u64 = $1;
- $$ = brw_imm_q(u64);
+ $$ = brw_imm_q($1);
break;
case BRW_REGISTER_TYPE_UQ:
- u64 = $1;
- $$ = brw_imm_uq(u64);
+ $$ = brw_imm_uq($1);
break;
case BRW_REGISTER_TYPE_DF:
$$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
$4.vstride,
$4.width,
$4.hstride,
- $5.swizzle,
+ $5,
WRITEMASK_X);
$$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
$4.vstride,
$4.width,
$4.hstride,
- $5.swizzle,
+ $5,
WRITEMASK_X);
}
| srcarcoperandex
directmsgreg:
MSGREG subregnum
{
- $$ = brw_message_reg($1);
+ $$.file = BRW_MESSAGE_REGISTER_FILE;
+ $$.nr = $1;
$$.subnr = $2;
}
;
error(&@1, "Mask register number %d"
" out of range\n", $1);
- $$ = brw_mask_reg($2);
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_MASK;
+ $$.subnr = $2;
}
;
notifyreg:
NOTIFYREG subregnum
{
- if ($1 > 0)
- error(&@1, "Notification register number %d"
- " out of range\n", $1);
-
int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
if ($2 > subnr)
error(&@2, "Notification sub register number %d"
" out of range\n", $2);
- $$ = brw_notification_reg();
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_NOTIFICATION_COUNT;
$$.subnr = $2;
}
;
error(&@2, "control sub register number %d"
" out of range\n", $2);
- $$ = brw_cr0_reg($2);
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_CONTROL;
+ $$.subnr = $2;
}
;
threadcontrolreg:
THREADREG subregnum
{
- if ($1 > 0)
- error(&@1, "Thread control register number %d"
- " out of range\n", $1);
-
if ($2 > 7)
error(&@2, "Thread control sub register number %d"
" out of range\n", $2);
- $$ = brw_tdr_reg();
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_TDR;
$$.subnr = $2;
}
;
$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
$$.nr = BRW_ARF_TIMESTAMP;
+ $$.subnr = $2;
}
;
error(&@1, "Channel enable register number %d"
" out of range\n", $1);
- $$ = brw_mask_reg($2);
+ $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+ $$.nr = BRW_ARF_MASK;
+ $$.subnr = $2;
}
;
/* Regions */
dstregion:
- %empty { $$ = -1; }
+ %empty
+ {
+ $$ = BRW_HORIZONTAL_STRIDE_1;
+ }
| LANGLE exp RANGLE
{
if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
region:
%empty
{
- $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
+ $$ = stride($$, 0, 1, 0);
}
| LANGLE exp RANGLE
{
if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
error(&@2, "Invalid VertStride %d\n", $2);
- $$ = stride($$, $2, BRW_WIDTH_1, 0);
+ $$ = stride($$, $2, 1, 0);
}
| LANGLE exp COMMA exp COMMA exp RANGLE
{
error(&@4, "Invalid Horizontal stride in"
" region_wh %d\n", $4);
- $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
+ $$ = stride($$, 0, $2, $4);
+ $$.vstride = BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL;
}
;
writemask:
%empty
{
- $$= brw_set_writemask($$, WRITEMASK_XYZW);
+ $$ = WRITEMASK_XYZW;
}
| DOT writemask_x writemask_y writemask_z writemask_w
{
- $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
+ $$ = $2 | $3 | $4 | $5;
}
;
swizzle:
%empty
{
- $$.swizzle = BRW_SWIZZLE_NOOP;
+ $$ = BRW_SWIZZLE_NOOP;
}
| DOT chansel
{
- $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
+ $$ = BRW_SWIZZLE4($2, $2, $2, $2);
}
| DOT chansel chansel chansel chansel
{
- $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
+ $$ = BRW_SWIZZLE4($2, $3, $4, $5);
}
;
projects / mesa.git / blobdiff