package sifive.blocks.devices.gpio
import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksBundle,
- HasTopLevelNetworksModule
-}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.TLFragmenter
+import freechips.rocketchip.util.HeterogeneousBag
-case object PeripheryGPIOKey extends Field[GPIOParams]
+case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
-trait HasPeripheryGPIO extends HasTopLevelNetworks {
+trait HasPeripheryGPIO extends HasSystemNetworks {
val gpioParams = p(PeripheryGPIOKey)
- val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams))
- gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := gpio.intnode
+ val gpios = gpioParams map {params =>
+ val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
+ gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+ intBus.intnode := gpio.intnode
+ gpio
+ }
}
-trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
- val outer: HasPeripheryGPIO
- val gpio = new GPIOPortIO(outer.gpioParams)
+trait HasPeripheryGPIOBundle {
+ val gpio: HeterogeneousBag[GPIOPortIO]
}
-trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
+trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGPIOBundle {
val outer: HasPeripheryGPIO
- val io: HasPeripheryGPIOBundle
- io.gpio <> outer.gpio.module.io.port
+ val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))))
+
+ (gpio zip outer.gpios) foreach { case (io, device) =>
+ io <> device.module.io.port
+ }
}