package sifive.blocks.devices.i2c
import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{TopNetwork,TopNetworkModule}
-import uncore.tilelink2.TLFragmenter
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
-trait PeripheryI2C {
- this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
- val i2c = i2cConfigs.zipWithIndex.map { case (c, i) =>
- val i2c = LazyModule(new TLI2C(c))
- i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := i2c.intnode
+case object PeripheryI2CKey extends Field[Seq[I2CParams]]
+
+trait HasPeripheryI2C { this: BaseSubsystem =>
+ val i2cParams = p(PeripheryI2CKey)
+ val i2c = i2cParams.zipWithIndex.map { case(params, i) =>
+ val name = Some(s"i2c_$i")
+ val i2c = LazyModule(new TLI2C(pbus.beatBytes, params)).suggestName(name)
+ pbus.toVariableWidthSlave(name) { i2c.node }
+ ibus.fromSync := i2c.intnode
i2c
}
}
-trait PeripheryI2CBundle {
- this: { val i2cConfigs: Seq[I2CConfig] } =>
- val i2cs = Vec(i2cConfigs.size, new I2CPort)
+trait HasPeripheryI2CBundle {
+ val i2c: Vec[I2CPort]
}
-trait PeripheryI2CModule {
- this: TopNetworkModule {
- val i2cConfigs: Seq[I2CConfig]
- val outer: PeripheryI2C
- val io: PeripheryI2CBundle
- } =>
- (io.i2cs zip outer.i2c).foreach { case (io, device) =>
+trait HasPeripheryI2CModuleImp extends LazyModuleImp with HasPeripheryI2CBundle {
+ val outer: HasPeripheryI2C
+ val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
+
+ (i2c zip outer.i2c).foreach { case (io, device) =>
io <> device.module.io.port
}
}