package sifive.blocks.devices.mockaon
import Chisel._
-import config.Field
-import coreplex.CoreplexRISCVPlatform
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksBundle,
- HasTopLevelNetworksModule
-}
-import uncore.tilelink2.{IntXing, TLAsyncCrossingSource, TLFragmenter}
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.SynchronizerShiftReg
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.devices.debug.HasPeripheryDebug
+import freechips.rocketchip.devices.tilelink.HasPeripheryClint
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.util.ResetCatchAndSync
case object PeripheryMockAONKey extends Field[MockAONParams]
-trait HasPeripheryMockAON extends HasTopLevelNetworks {
- val coreplex: CoreplexRISCVPlatform
-
+trait HasPeripheryMockAON extends HasPeripheryBus
+ with HasInterruptBus
+ with HasPeripheryClint
+ with HasPeripheryDebug {
// We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain.
val mockAONParams= p(PeripheryMockAONKey)
- val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams))
- val aon_int = LazyModule(new IntXing)
- aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node))
- aon_int.intnode := aon.intnode
- intBus.intnode := aon_int.intnode
+ val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
+ aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
+ ibus.fromAsync := aon.intnode
}
-trait HasPeripheryMockAONBundle extends HasTopLevelNetworksBundle {
- val aon = new MockAONWrapperBundle()
+trait HasPeripheryMockAONBundle {
+ val aon: MockAONWrapperBundle
+ def coreResetCatchAndSync(core_clock: Clock) = {
+ ResetCatchAndSync(core_clock, aon.rsts.corerst, 20)
+ }
}
-trait HasPeripheryMockAONModule extends HasTopLevelNetworksModule {
+trait HasPeripheryMockAONModuleImp extends LazyModuleImp with HasPeripheryMockAONBundle {
val outer: HasPeripheryMockAON
- val io: HasPeripheryMockAONBundle
+ val aon = IO(new MockAONWrapperBundle)
- io.aon <> outer.aon.module.io
+ aon <> outer.aon.module.io
// Explicit clock & reset are unused in MockAONWrapper.
// Tie to check this assumption.
outer.aon.module.clock := Bool(false).asClock
outer.aon.module.reset := Bool(true)
- outer.coreplex.module.io.rtcToggle := outer.aon.module.io.rtc.asUInt.toBool
+ // Synchronize the external toggle into the clint
+ val rtc_sync = SynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc"))
+ val rtc_last = Reg(init = Bool(false), next=rtc_sync)
+ val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
+
+ outer.clint.module.io.rtcTick := rtc_tick
+ outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
}