package sifive.blocks.devices.mockaon
import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
-import sifive.blocks.util.{DeglitchShiftRegister, ResetCatchAndSync}
-import util._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+import sifive.blocks.devices.pinctrl.{EnhancedPin}
+import sifive.blocks.util.{DeglitchShiftRegister}
+
/* The wrapper handles the Clock and Reset Generation for The AON block itself,
and instantiates real pad controls (aka pull-ups)*/
class MockAONWrapperPMUIO extends Bundle {
- val dwakeup_n = new GPIOPin()
- val vddpaden = new GPIOPin()
+ val dwakeup_n = new EnhancedPin()
+ val vddpaden = new EnhancedPin()
}
-class MockAONWrapperPadsIO extends Bundle {
- val erst_n = new GPIOPin()
- val lfextclk = new GPIOPin()
+class MockAONWrapperPins extends Bundle {
+ val erst_n = new EnhancedPin()
+ val lfextclk = new EnhancedPin()
val pmu = new MockAONWrapperPMUIO()
}
class MockAONWrapperBundle extends Bundle {
- val pads = new MockAONWrapperPadsIO()
+ val pins = new MockAONWrapperPins()
val rsts = new MockAONMOffRstIO()
}
-class MockAONWrapper(c: MockAONConfig)(implicit p: Parameters) extends LazyModule {
+class MockAONWrapper(w: Int, c: MockAONParams)(implicit p: Parameters) extends LazyModule {
val node = TLAsyncInputNode()
val intnode = IntOutputNode()
- val aon = LazyModule (new MockAON(c)(p))
+ val aon = LazyModule(new TLMockAON(w, c))
// We only need to isolate the signals
// coming from MOFF to AON,
val in = node.bundleIn
val ip = intnode.bundleOut
val rtc = Clock(OUTPUT)
+ val ndreset = Bool(INPUT)
}
val aon_io = aon.module.io
- val pads = io.pads
+ val pins = io.pins
// -----------------------------------------------
// Generation of aonrst
// -----------------------------------------------
// ERST
- val erst = ~ GPIOInputPinCtrl(pads.erst_n, pue = Bool(true))
+ val erst = ~pins.erst_n.inputPin(pue = Bool(true))
aon_io.resetCauses.erst := erst
aon_io.resetCauses.wdogrst := aon_io.wdog_rst
// Note that the actual mux lives inside AON itself.
// Therefore, the lfclk which comes out of AON is the
// true clock that AON and AONWrapper are running off of.
- val lfextclk = GPIOInputPinCtrl(pads.lfextclk, pue=Bool(true))
+ val lfextclk = pins.lfextclk.inputPin(pue=Bool(true))
aon_io.lfextclk := lfextclk.asClock
// Drive AON's clock and Reset
val lfclk = aon_io.lfclk
val aonrst_catch = Module (new ResetCatchAndSync(3))
- aonrst_catch.reset := erst | aon_io.wdog_rst
+ aonrst_catch.reset := erst | aon_io.wdog_rst | io.ndreset
aonrst_catch.clock := lfclk
aon.module.reset := aonrst_catch.io.sync_reset
isolation.module.io.iso_in := Bool(true)
//--------------------------------------------------
- // PMU <--> pads Interface
+ // PMU <--> pins Interface
//--------------------------------------------------
- val dwakeup_n_async = GPIOInputPinCtrl(pads.pmu.dwakeup_n, pue=Bool(true))
+ val dwakeup_n_async = pins.pmu.dwakeup_n.inputPin(pue=Bool(true))
val dwakeup_deglitch = Module (new DeglitchShiftRegister(3))
dwakeup_deglitch.clock := lfclk
dwakeup_deglitch.io.d := ~dwakeup_n_async
aon.module.io.pmu.dwakeup := dwakeup_deglitch.io.q
- GPIOOutputPinCtrl(pads.pmu.vddpaden, aon.module.io.pmu.vddpaden)
+ pins.pmu.vddpaden.outputPin(aon.module.io.pmu.vddpaden)
//--------------------------------------------------
// Connect signals to MOFF