package sifive.blocks.devices.pwm
import Chisel._
-import config.Field
-import diplomacy.{LazyModule,LazyMultiIOModuleImp}
-import rocketchip.HasSystemNetworks
-import uncore.tilelink2.TLFragmenter
-import util.HeterogeneousBag
-
-import sifive.blocks.devices.gpio._
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.util.HeterogeneousBag
+import sifive.blocks.devices.pinctrl.{Pin}
class PWMPortIO(val c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
-class PWMPinsIO(val c: PWMParams) extends Bundle {
- val pwm = Vec(c.ncmp, new GPIOPin)
+class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
+
+ val pwm: Vec[T] = Vec(c.ncmp, pingen())
+
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
}
-class PWMGPIOPort(val c: PWMParams) extends Module {
- val io = new Bundle {
- val pwm = new PWMPortIO(c).flip()
- val pins = new PWMPinsIO(c)
- }
- GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
+class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends PWMSignals[T](pingen, c) {
+
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
+
+ def fromPort(port: PWMPortIO) {
+ (pwm zip port.port) foreach {case (pin, port) =>
+ pin.outputPin(port)
+ }
+ }
}
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
-trait HasPeripheryPWM extends HasSystemNetworks {
+trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
val pwmParams = p(PeripheryPWMKey)
val pwms = pwmParams map { params =>
- val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
- pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := pwm.intnode
+ val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
+ pwm.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := pwm.intnode
pwm
}
}
trait HasPeripheryPWMBundle {
- val pwms: HeterogeneousBag[PWMPortIO]
+ val pwm: HeterogeneousBag[PWMPortIO]
- def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMPinsIO] = pwms.map { p =>
- val pins = Module(new PWMGPIOPort(p.c))
- pins.io.pwm <> p
- pins.io.pins
- }
}
trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
val outer: HasPeripheryPWM
- val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+ val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
- (pwms zip outer.pwms) foreach { case (io, device) =>
+ (pwm zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}